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Visitor
Visitor
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Registered: ‎08-20-2010

PCI express Current link is not work at the available maxium Cabilities link on ML605

Hey,

i've genereted several PCI Express IP in oder to test the data transfert performance rate.
I've generated many design using xapp1052.pdf. All the IP that I've tested are linking in Gen1 x1 even if the design capabilities link is set to Gen2 x4 or Gen1 x8. Of course I've done many test moving the J42 jumper from x1 to x4 and x8.

The current link is always working at gen1 x1. Using PciTree software I can monitore that the capabilities link is set to Gen2 x4 or Gen1 x8.

So I would like to know if someone has already get this problem....
(for information, durring all my test, the ML605 board is plugged in x16 PCI express slot in x86 architecture)

 

In Attachement, I've added my test resuslts in Gen1 x1. I don't really understand these results figure. As you can see, when I read, I've got a 1771.63 Mbps data rate and when I write the data rate is down to 155.06 Mbps. Durring the reading phase, the data transfert rate should be around 2 Gb/s right ? so why these strange values ? I can also quote that the cycle is not the same for reading and writing.

 

Thanks

test_perf_dma_pcie.bmp
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