09-29-2020 07:59 AM
I would appreciate help with an AXI Lite simulation for the XDMA. I have been searching the Xilinx forum and have not been successful for an example with a simulation for the XDMA IP with AXI Lite Master interface that sends read and write traffic from the AXI Lite master interface to the slave logic attached to it. I saw the XDMA example design and ran the simulation for it. However, it seems to exercise the XDMA feature only.
Would you be able to help me with finding an example testbench that has read and write functions that allow me to access the AXI Lite slave logic connected to the AXI Lite Master Interface of the XDMA.
09-30-2020 02:54 PM
10-01-2020 07:55 AM
Good morning deepeshm,
Yes, I saw the example design in pg195. I'm using this one: Fig 24 - AXI4-Stream Example with PCIe to DMA Bypass Interface and PCIe to AXILite Master Enabled which also has a block ram attached to the axi4-lite master on the XDMA. I'm assuming the AXI4-lite accesses to the blockram should be equivalent to the Figure 22 that you suggested.
I'm assuming the AXI4-lite master is on BAR0 so I modified the sample_tests.vh for the end of the dma test to write a few 32-bit words to the block ram such as 0x600d_f00d and 0xb0b0_cafe shown below using the tasks provide in the example design from the pci_exp_usrapp_tx.v:
However, when I ran the testbench in the waveform window at the times listed in the tx.dat I did not see any activity on the axi4-lite bus attached to the blockram when I was invoking the above tasks. When I check the tx.dat the file did report the transactions.
Would you be able to see if I am using the tasks correctly in sample_tasks.vh starting at line 165 or if I should be using TSK_TX_MEMORY_WRITE_32 instead of the
TSK_TX_BAR_WRITE(3'b0, 32'h200, 8'd0, 3'b0, 32'hb0b0_cafe);
Or, is it a matter with the way the block ram was mapped to the BARs in the sim causing me not to see any activity in the waveform window?
Also, in the TSK_TX_BAR_WRITE(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC, pattern);
what do the tag and traffic class do for the simulation?
I had to change the extension of the sample_tests.vh and tx.dat in order to upload the files.
10-05-2020 04:24 PM
Just wondering if you had a chance to take a look at my question about the use of the tasks for the access of the axi-lite interface on the XDMA to be able to write to user logic attached to the Master AXI4-lite interface.
Thank you for your help,