PCIE:BARS vs. AXI:BARS in AXI Memory Mapped to PCI Express

[daryon]

Hi,

I am using Vivado 2017.3 targeting a ZC706 board.

I have a design including the "AXI Memory Mapped to PCI Express" (axi_pcie_0) module to enable PCIe. I am reading this document to figure out what is the different between PCIE:BARS and AXI:BARS? but I am confused since the explanation was not clear to me! Looking at Figure 8 and Figure 11 in that document, can anyone explain me what is the difference and how it works?

THanks in advance for your replies and kind helps.

Bests,

Daryon,

[necare81 · Accepted solution]

The difference is basically the direction of the transfer.

Your host will system configure the PCI BARs that you enable in the configuration shown in Figure 7 (but not the AXI-PCIe translation) with some address of its choosing.  Lets say that is the value 0xF000_0000.

Now say you have an IP in your FPGA that you have configured for AXI address 0x0900_0000 and this IP needs 16K of address space.

Now you want to access a register at address 0x100 in that IP.  What physical address does the host software need to use?  That depends on how you configure the translation and the BAR size in the PCIe IP.

Option 1:  No translation - the AXI output address will be (the host software address - the PCI BAR value). So to reach an address at 0x900_0100.  Host software address must be 0xF900_0100 and we must assign a BAR size of 256M, the range 0xF000_000 to 0xFF00_0000 to that PCIe device.

Option 2:  Translation is set as 0x0900_0000.  The AXI output address will be (the host software address - the PCI BAR value)+Translation value.  Host software would use the address 0xF000_0100 and we can use a BAR size  of 16K with the values 0xF000_0000 to 0xF000_FFFF.

If you have full control over the addresses and and need PCIe access to all IPs on the AXI bus the translation isn't needed in that direction.  But if you need only select IPs at already determined ranges you can use the translation offset to have smaller BAR spaces assigned.

The AXI:BARs basically work the same for generating the address in the FPGA to hit a known physical address in the host system

[daryon]

Dear @necare81,

Excellent explanation! Proud of you ! It is now very clear to me! Thank you so much for your great teaching.

I accepted your answer  as a solution to my thread + 1 KUDO as a small gift! :)

Thank you!