07-20-2021 01:16 AM
We are trying to enable the PCIE Gen3 interface using GTH path on PL side of the Ultrascale+ MPSOC 5EV device.
We have generated the PCIE Integrated Block from IP catalog and kept the default settings (Gen 1 and one lane ) and generated the example design. In simulations we can see the user link signal going up but when in the hardware this signal is not coming up.
Our Hardware is connected to actual PC through a SAMTEC PCIE cable and we have verified that the 100MHz clock is coming the Host. sys_rst_n signal is not connected in the hardware and is generated internally after 5 secs of power on.
We dont see any PCIe device in the device manager after loading the bit file.
Please suggest how can we debug the same. We are presently going through the below link to debug
We are new to this interface and this is the first time we are using the PCIE so any help or guidance on this will be very helpful
07-21-2021 05:59 AM
Hi @sutej ,
You need to do few check points
1) Verify is the boards PCIe finger is slotted properly on host machine and not loose.
2) Load the bitstream onto board through Vivado Hardware manger.
3) Once the bit file is loaded onto board you may need to reboot the host machine keep in mind that boards is not powered off during this process.
4) After reboot host should detect the Xilinx PCIe controller device. In linux host try the below command
lspci -v |grep -i xilinx
5) If above step is success ful that means you are good to use it else you have to check the ltssm file generated which will record the issue in link training. These files can be found in design implementation folder.
07-24-2021 12:21 AM
We have not connected the PERST signal from PCIe edge connector to the FPGA.
But we are generating sys_rst signal internally. Will this be a problem ?