06-07-2019 09:25 AM
I have a question on how AXI_ACLK clocks are set up in PCIE XDMA core v4.1 (vivado 2018.3). I have the core set up for VC709. The AXI clock frequency is fixed at 250MHz since the lane width is x8 and maximum link speed is set to 8.0GT/s.
I am using two descriptor bypass C2H interfaces which use axi_aclk running at 250MHz. I also have AXI Lite Master interface enabled for and the BAR size is set to 1M
The question is whether both C2H axi-streaming and AXI-Lite Master interfaces use same axi_aclk? Is it possible to use slower version of axi_aclk for AXI-Lite Master interface? 250MHz for the AXI-Lite Master is going to cause problems for us downstream.
Thanks in advance.
06-13-2019 08:02 PM
Is there a problem with 250 MHz?
The clock should be connected internally in the recent core. PG describes as below:
AXI Bridge for PCIe Gen3 only:
aclk for the S_AXI_CTL interface. Recommended to be
driven by the axi_aclk output. axi_ctl_aclk is a derived
clock from the TXOUTCLK pin from the GT block; it is not
expected to run continuously while axi_ctl_aresetn is
Note: This pin is for legacy use mode only. By default, new IP
generation will have this clock pin internally driven by the IP.
Use axi_aclk pin to clock the design.
(( Page13, PG194))
06-14-2019 05:22 AM
Thank you for the reply.
There is no problem with 250MHz as such although it's not a continuous clock which is troublesome. In PCI XDMA core (PG195 instead of PG194), it seems there is only clock avaialble : axi_aclk. We use that clock for axi-streaming as well as axi-lite master/slave interfaces. But we have a large mux that generates a lot of FPGA registers using axi-lite master interface and typically would like to run that inteface slower (say 100MHz). From your answer, it sounds like that is not an option.