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spman2
Visitor
Visitor
10,063 Views
Registered: ‎01-01-2013

PCIE device is not detected (virtex-7)

Hi I want to implement PCI Express on a Hitechglobal HTG-703 (Virtex-7 xc7vx690t) board. The problem is that PC does not detect a PCI Express after implementing the design (and rebooting system). In order to implement PCI Express, I added PCI Express core in Vivado 2013.4. The core is customized as follows:

 

PCI Express end point device

PCIE Block Location: X0Y1

Lane width: 4

Reference Clock Frequecy: 100 MHz

Maximum Link Speed: 2.5 GT/s

Enable Slot Clock Configuration: Enabled

 

Then I opened example design of the core and assigned sys_clk_p and sys_reset_n to U10 and AV29 respectively. U10 is the MGT reference clock which is connected to the output of the PCI Express PLL chip. On the other hand this chip is connected to the output clock of PCIE edge and so I think “Slot Clock Configuration” must be enabled (right?). AV29 is connected to reset signal of PCIE edge. After synthesizing I checked all RX and Tx locations according to schematic of the board and all of them were ok. (There is not anything about location of PCIE core and RX TX locations in the constraint file! Shoud I add these constraints to the constraint file?)

 

I expect that an unknown PCI Express device is detected after rebooting. But the device is not detected.

Could anyone please help me?

 

Thanks in advance

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kotir
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10,060 Views
Registered: ‎02-03-2010

Hi,

 

Can you check if you can download the referance deisgn bit file of the board you are using from Xilinx site ?

There are example designs given for each board on boards page of xilinx site.

 

Regards,

KR

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spman2
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Registered: ‎01-01-2013

I couldn't find any PCIE example design for HTG-703 board.
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kotir
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Scholar
10,050 Views
Registered: ‎02-03-2010

 

Hi,

 

Okay you are using third party board. sorry for the overlook. I thought you are using the xilixn board.


Still if the board vendor provided any referance files for PCIe , can you try them ?

Other wise you need to check for link issues.

 

Below is the link debugging guide.

 

http://www.xilinx.com/support/answers/56616.html

 

Regards,

KR

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