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Adventurer
Adventurer
983 Views
Registered: ‎11-23-2017

PCIE example design problem

Hi,

 

I am trying to run the example design of DMA Subsystem for PCI Express on a ZC706 board.

I generated a Gen-2 X4 core using IP catalog. Then, I opened its example design and added constraints for sys_clk and sys_rst_n ports according to the board's schematic, i.e. sys_clk => MGTREFCLK0 of Bank 112 (N8, N7)  and sys_rst_n => PCIE_PERST (AK23). After synthesizing, I checked the PCIE data signals in the synthesized design. They all are at the right location according to the schematic.

However, when I program the FPGA using the example design and turn on the PC, the card is not recognized. I use Windows 7 and search for the new device in Device Manager.

It should also be noted that J19 jumper is on X4 (4 lanes) configuration.

 

Could anyone please help me?

 

Thanks in advance.

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Xilinx Employee
Xilinx Employee
947 Views
Registered: ‎12-10-2013

Hi @mo69_hoseini,

 

Could you insert a JTAG debugger from the Debug Options menu and collect the data as described in:

https://www.xilinx.com/support/answers/68134.html

 

This should now be available in the 7-series devices.

 

 

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Adventurer
Adventurer
934 Views
Registered: ‎11-23-2017

Thanks @bethe,

 

Unfortunately, the core does not have any debug options in Vivado 2017.2 :(

 

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Moderator
Moderator
925 Views
Registered: ‎02-16-2010

Can you try with axi pcie IP? I find this IP has JTAG debugger option to help with the debug.

axi_pcie_jtag_debugger.JPG

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Adventurer
Adventurer
881 Views
Registered: ‎11-23-2017

It worked on another motherboard! Thanks again.
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