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Voyager
Voyager
4,028 Views
Registered: ‎01-28-2008

PCIE v1.5 X8 Gen2 not supported on LX240T-1?

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Hi folks,

 

  I have no problem generating a PCIE v1.5 X8 Gen2 core on Virtex6-LX240T speed -2, but I cannot do the same on a speed -1 device. The 5.0GT/s option gets grayed out when the device is speed -1.

  Is it not supported? does it have timing issues or is it a bug in the coregen PCIE generator GUI?

 

  Our first batch of prototypes is in house with -1 devices, and we'd like to port our DMA controller from Gen1 core to Gen2. The PCB was designed with this in mind.

 

  What would happen if I generate for speed -2 but run it on a -1 device, given it passes timing?

 

Thanks in advance!

-Pat

 

https://tuxengineering.com
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Xilinx Employee
Xilinx Employee
4,757 Views
Registered: ‎08-13-2007

Re: PCIE v1.5 X8 Gen2 not supported on LX240T-1?

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Short story: no, yes, no, bad

 

longer one: The V6 -1 and -1L parts do not support Gen2 x8. They can do Gen2 x4 or Gen1 x8. They are not fast enough to reliably run the data demux on the backend of the wrapper for the Gen2 x8 configuration.

 

If you try it, you may get lucky with enough PVT (process/voltage/temperature) margin in a lab environment. But it isn't supported because it won't reliably work. And please don't do this on a production design.

You also can not reliably run slower parts using a design targeted to a faster part. For one reason, par quits when it meets timing - so even if it could have worked on the right speed grade (and took a little longer to implement), it likely quit when it met the goals you gave it, but not the required more ambitious goals. The results of the trce STA doesn't apply on the slower parts -the part profiles and corresponding speed files are different. I've seen enough of this when people did it accidentally and didn't initially notice it because the part was heat-sinked. And then spent a long time chasing "whack a mole" type problems that moved around in the design every new iteration (and between boards) because the parts weren't fast enough to meet the assumptions of the design and timing analysis. When they targeted the design to the correct speed grade, par took a little longer (it had to try harder) and the design worked.

 

But the specific analysis went into the PCIe configuration and the -1/-1L parts aren't fast enough across PVT.

 

bt 

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Xilinx Employee
Xilinx Employee
4,758 Views
Registered: ‎08-13-2007

Re: PCIE v1.5 X8 Gen2 not supported on LX240T-1?

Jump to solution

Short story: no, yes, no, bad

 

longer one: The V6 -1 and -1L parts do not support Gen2 x8. They can do Gen2 x4 or Gen1 x8. They are not fast enough to reliably run the data demux on the backend of the wrapper for the Gen2 x8 configuration.

 

If you try it, you may get lucky with enough PVT (process/voltage/temperature) margin in a lab environment. But it isn't supported because it won't reliably work. And please don't do this on a production design.

You also can not reliably run slower parts using a design targeted to a faster part. For one reason, par quits when it meets timing - so even if it could have worked on the right speed grade (and took a little longer to implement), it likely quit when it met the goals you gave it, but not the required more ambitious goals. The results of the trce STA doesn't apply on the slower parts -the part profiles and corresponding speed files are different. I've seen enough of this when people did it accidentally and didn't initially notice it because the part was heat-sinked. And then spent a long time chasing "whack a mole" type problems that moved around in the design every new iteration (and between boards) because the parts weren't fast enough to meet the assumptions of the design and timing analysis. When they targeted the design to the correct speed grade, par took a little longer (it had to try harder) and the design worked.

 

But the specific analysis went into the PCIe configuration and the -1/-1L parts aren't fast enough across PVT.

 

bt 

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Voyager
Voyager
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Registered: ‎01-28-2008

Re: PCIE v1.5 X8 Gen2 not supported on LX240T-1?

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Hi Timpe,

 

  Thanks for your prompt and insightful response.

 

  What I meant on generating for a faster speed  is the core itself, but then placing this core in the main design and implement it as speed -1, matching the device. Thanks for the explanation though; we've had such instances in the past, where accidentally we were targetting a faster device and got strange functionality, just as you explained.

  Well, I suppose our first batch will be Gen1. Future revs will include the -2 parts and be Gen2-capable.

 

Thanks again!

-Pat

 

https://tuxengineering.com
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