PCIe 3.0 Core

[tpaler01@harris.com]

I’ve created a  PCIe 3.0 Core for and Ultrascale device.  One of the output signals is user_link_up.  I can’t find a description of this signal in PG194 (AXI Bridge for PCI Express Gen3 v3.0), and only brief mentions of the signal in search on the Xilinx site.

Can you give some description of the signal?

[deepeshm]

Please check PG156.

The link below is for 7-series but the theory applies. Please review the attached doc in the AR as well.

https://www.xilinx.com/support/answers/56616.html

Thanks.