02-28-2020 10:51 AM
I have been running Ultrascale PCIe 3.0 core example design simulation using either Vivado's simulator and Modelsim. Example design with sample_smoke_test0 testbench fired on both simulators.
However, the strange thing is that on Vivado simulator testbench running successfully and gets correct complete frames on Config 0 TLP requests from RP. But when I am using same files with Modelsim, I didn't receive any correct response from EP on RP config 0 read TLP, and simulation finished with time out.
This is rx.dat file content
[ 140960000] : Completion Without Data Frame
Traffic Class: 0x0
Completer Id: 0x0000
Completion Status: 0x0
Requester Id: 0x0000
Attached is the log windows of Modelsim.
Please help, I have spend one week on debugging, and couldn't finish it yet!
03-02-2020 12:13 AM
Please let us know the following:
1. Vivado Version
2. Core Configuration: Speed/Width
3. Is it the default example design without any modification?
This might have already been checked, if not please check by increasing the simulation time.
03-02-2020 02:18 AM
Thank you for reply!
Here are more info:
Vivado version: 2018.1
Simulation in Modelsim runs for some more time and then finished with timeout, because wrong TLP received from EP.
I have attached screenshot.
I have found that there are some configuration input pins which are not connected for RP PCIe instance. Can this be the reason of mismatch?