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gevorgo
Visitor
Visitor
407 Views
Registered: ‎11-17-2018

PCIe 3p0 Example Design

Hi,

I have been running Ultrascale PCIe 3.0 core example design simulation using either Vivado's simulator and Modelsim. Example design with sample_smoke_test0 testbench fired on both simulators.

However, the strange thing is that on Vivado simulator testbench running successfully and gets correct complete frames on Config 0 TLP requests from RP. But when I am using same files with Modelsim, I didn't receive any correct response from EP on RP config 0 read TLP, and simulation finished with time out. 

This is rx.dat file content

[ 140960000] : Completion Without Data Frame

Traffic Class: 0x0
TD: 0
EP: 0
Attributes: 0x0
Length: 0x000
Completer Id: 0x0000
Completion Status: 0x0
Requester Id: 0x0000
Tag: 0x00

Attached is the log windows of Modelsim.

Please help, I have spend one week on debugging, and couldn't finish it yet!

Capture.PNG
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2 Replies
deepeshm
Xilinx Employee
Xilinx Employee
315 Views
Registered: ‎08-06-2008

Please let us know the following:

1. Vivado Version

2. Core Configuration: Speed/Width

3. Is it the default example design without any modification?

This might have already been checked, if not please check by increasing the simulation time.

Thanks.

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gevorgo
Visitor
Visitor
298 Views
Registered: ‎11-17-2018

Thank you for reply!

Here are more info:

Vivado version: 2018.1

Speed 8Gbit

Width 256bits

Simulation in Modelsim runs for some more time and then finished with timeout, because wrong TLP received from EP.

I have attached screenshot.

I have found that there are some configuration input pins which are not connected for RP PCIe instance. Can this be the reason of mismatch?

Thanks.

 

 

Capture2.PNG
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