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avinashc
Explorer
Explorer
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Registered: ‎10-09-2018

PCIe-Artix 7 Simulation problem - EP MEM not getting data from packets

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Hello,

system- Artix7 Xc7a100t, ISE 14.7, Win10-64 bit

 

I am using example design of PCIe core and running the simulation.

pcie_rx and pcie_tx diffrential pair get the data but in Endpoint mem BAR I am not receiving any data.

1.jpg

So my question is:

1) How many packets are sending by pkt generation file.

2) Is there any requirement of min DWORD to be sent to mem by pkt generations?

3) why my EP MEM is not getting the data?

 

Thanks!

Avinash

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avinashc
Explorer
Explorer
516 Views
Registered: ‎10-09-2018

Hello,

It is working now.

Actually even after user_lnk goes high it takes 50-80us extra time to get data on simulation , I was not going till that time earlier. 

Thank You!

 

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2 Replies
liy
Xilinx Employee
Xilinx Employee
547 Views
Registered: ‎08-02-2007

There are several branch for the simulation example. 

you can find more info in the sample_test.vh file. If the test only includes the config access then there is no transaction on the BARs


you could try to run the below test to verify the memory access

testname == "pio_writeReadBack_test0"

 

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avinashc
Explorer
Explorer
517 Views
Registered: ‎10-09-2018

Hello,

It is working now.

Actually even after user_lnk goes high it takes 50-80us extra time to get data on simulation , I was not going till that time earlier. 

Thank You!

 

View solution in original post