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Observer
Observer
4,542 Views
Registered: ‎10-22-2008

PCIe Blk Plus v1.9 in Apple Mac Pro

Hi at all,

does anyone have experience with the PCIe Block Plus v1.9(Virtex-5 FX70T) in Apple Mac Pro (from 2006)?

 

My situation: our own PCIe x8 board passed the first basic PCIe tests on two different intel-based mainboards with Windows XP. No problems.

But if I plug the same board into the Mac Pro, it hangs during boot. The Display remains black and on the board the CPU B failed LED is on.

With ChipScope I can see that the link is up.

 

Is the core config ok?

 

# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vfx70t
SET devicefamily = virtex5
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Endpoint_Block_Plus_for_PCI_Express family Xilinx,_Inc. 1.9
# END Select
# BEGIN Parameters
CSET acceptable_l0_latency=No_limit
CSET acceptable_l1_latency=No_limit
CSET advanced_flow_control_credit=Completion_Credits
CSET aux_max_current=0mA
CSET bar0_64bit=false
CSET bar0_enabled=true
CSET bar0_prefetchable=false
CSET bar0_scale=Megabytes
CSET bar0_size=4
CSET bar0_type=Memory
CSET bar0_value=FFC00000
CSET bar1_64bit=false
CSET bar1_enabled=false
CSET bar1_prefetchable=false
CSET bar1_scale=Kilobytes
CSET bar1_size=64
CSET bar1_type=IO
CSET bar1_value=00000000
CSET bar2_64bit=true
CSET bar2_enabled=true
CSET bar2_prefetchable=false
CSET bar2_scale=Megabytes
CSET bar2_size=32
CSET bar2_type=Memory
CSET bar2_value=FE000004
CSET bar3_64bit=false
CSET bar3_enabled=false
CSET bar3_prefetchable=false
CSET bar3_scale=Kilobytes
CSET bar3_size=64
CSET bar3_type=IO
CSET bar3_value=FFFFFFFF
CSET bar4_64bit=false
CSET bar4_enabled=false
CSET bar4_prefetchable=false
CSET bar4_scale=Kilobytes
CSET bar4_size=64
CSET bar4_type=IO
CSET bar4_value=00000000
CSET bar5_enabled=false
CSET bar5_prefetchable=false
CSET bar5_scale=Kilobytes
CSET bar5_size=64
CSET bar5_type=IO
CSET bar5_value=00000000
CSET capabilities_register=0001
CSET capability_version=1
CSET cardbus_cis_pointer=00000000
CSET class_code_base=04
CSET class_code_interface=00
CSET class_code_sub=00
CSET class_code_value=040000
CSET component_name=pcie_x8_v1_9
CSET d0_pme_support=true
CSET d0_power_consumed=0
CSET d0_power_consumed_factor=0
CSET d0_power_dissipated=0
CSET d0_power_dissipated_factor=0
CSET d1_pme_support=false
CSET d1_power_consumed=0
CSET d1_power_consumed_factor=0
CSET d1_power_dissipated=0
CSET d1_power_dissipated_factor=0
CSET d1_support=false
CSET d2_pme_support=false
CSET d2_power_consumed=0
CSET d2_power_consumed_factor=0
CSET d2_power_dissipated=0
CSET d2_power_dissipated_factor=0
CSET d2_support=false
CSET d3_power_consumed=0
CSET d3_power_consumed_factor=0
CSET d3_power_dissipated=0
CSET d3_power_dissipated_factor=0
CSET d3cold_pme_support=false
CSET d3hot_pme_support=false
CSET device_capabilities_register=00000FC1
CSET device_id=0060
CSET device_port_type=PCI_Express_Endpoint_device
CSET device_specific_initialization=false
CSET enable_aspm_l1_support=false
CSET enable_slot_clock_cfg=true
CSET expansion_rom_bar=FFF00001
CSET expansion_rom_enabled=true
CSET expansion_rom_scale=Megabytes
CSET expansion_rom_size=1
CSET force_no_scrambling=false
CSET gt_debug_ports=false
CSET interface_freq=250_default
CSET lane_width=X8
CSET link_capabilities_register=0003F481
CSET max_payload_size=256_bytes
CSET maximum_link_speed=1
CSET maximum_link_width=8
CSET msi=1_vector
CSET reference_freq=100
CSET revision_id=00
CSET subsystem_id=0060
CSET subsystem_vendor_id=1A55
CSET trim_tlp_digest=true
CSET tx_diff_boost=true
CSET tx_diff_ctrl=800
CSET tx_pre_emphasis=52
CSET vendor_id=1A55
# END Parameters
GENERATE
# CRC: aa41af1

 


 

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2 Replies
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Xilinx Employee
Xilinx Employee
4,532 Views
Registered: ‎08-07-2007

Re: PCIe Blk Plus v1.9 in Apple Mac Pro

HI,

 

I would try the PIO example design that comes with the core. The fact that link is up but the machine is hanging leads me to believe that a completion time out is occurring. This might mean the machine is trying to read something you are not expecting. The PIO design will respond to all in coming reads so its a good design to rule this out.

 

Also, I noticed you are using a class code of 04 and subclass of 00 which indicates a video device. This might also cause some issues if the design is not properly responding. The PIO with the default settings uses the class code for a memory controller which is known to cause the least issues on most systems as far as start up.

 

-John

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Highlighted
Observer
Observer
4,510 Views
Registered: ‎10-22-2008

Re: PCIe Blk Plus v1.9 in Apple Mac Pro

Hi jayer

,

with the PIO design, the Mac Pro boots up. So, the class code doesn't have any effect because I tried the PIO design with our core configuration.

 

The Problem in our design is the missing support for the Expansion ROM (BAR6). No completions are generated. We will fix that.

 

Michael

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