03-20-2019 05:20 AM
Good day! We are using new AR65444 Linux drivers (https://www.xilinx.com/support/answers/65444.html) with CentOS Linux release 7 :
Xilinx_Answer_65444_Linux_Files_rel20180420.zip (Recommended Driver Version with improved error handling and more block partition for easy access)
We are using XDMA MM interface 64-bit AXI4, but we strongly need to use 32-bit data transactions.
We are interfacing with the driver-provided /dev/xdma/card0/c2h0 and /dev/xdma/card0/h2c0 devices
by using a simple C program with " fread(&value, 4, 1, pFile) " and " fwrite(&value, 4, 1, pFile); " accesses,
where 4 is a number of bytes (4 bytes = 32 bits) and value is the "unsigned int" 4 bytes = 32 bits variable.
However, despite that we see that the length of transfer is 4 bytes at the kernel logs for your driver :
file 0xffff9d62eb229100, priv 0xffff9d634cb8c0e8, buf 0x00007ffeac6ed1cc,4, pos 3221225472, W 0, 0-C2H0-MM.
0-C2H0-MM, len 4 sg cnt 1.
sw desc 0/1: 0xb8a95000, 0x4, ep 0xc0000000.
xfer, 4, ep 0xc0000004, done 0, sg 1/1.
transfer ffff9d6323f1c918, 4, ep 0xc0000000 compl, +0.
- still at the AXI4 interface waveform we could see that "arsize" and "awsize" are "11" (3) which stands for 8 bytes and the program reads two 32-bit registers instead of one.
This causes problems for us, e.g. when a read of a single 4 bytes register also touches the adjastent 4 byte register
which might be illegal to read.
Please advise, what we can do to ensure that the transactions are 32-bit = 4-byte size ?
03-20-2019 10:52 PM - edited 03-20-2019 10:53 PM
We are checking on this issue. We will get back to you as soon as we have an update. In the meantime, could you confirm which vivado version are you using?
03-21-2019 01:15 AM
We are using Vivado 2017.1 and couldn't update for hardware reasons.
04-09-2019 01:22 AM - edited 04-09-2019 01:22 AM
04-11-2019 08:10 AM
My apologies for the delay in getting back on this. Actually, this is a known behaviour. We have put the following note in PG194. This applies to the XDMA IP as well. We will update PG195 to reflect this.
always indicates that the requested size is equal to the Master AXI data width. The core drops the extra data when a
completion packet is formed and sent back to the requester.
In the write, awsize will always be equal to the bus size, we use the wstrb to make it narrower than that.So for writes, it should never touch the next register because the wstrb will be 0 on the bytes that are not used.
04-12-2019 05:36 AM
@deepeshm, Problem is: we have some 32-bit registers which are illegal to read, but they are situated between the other 32-bit registers. And we have encountered a situation where the 32-bit request to a driver to read a 32-bit register - inside a driver becomes transformed to a 64-bit request and therefore also touches the neighbour 32-bit register, which is illegal to read and doing that could cause the system malfunction. So it is not sufficient that the data read from the neighbour register will be discarded later - it should not have been read at all in the first place. Please fix this driver issue.
04-24-2019 05:47 AM