03-02-2020 03:08 AM - edited 03-02-2020 03:20 AM
I need to develop a PCIe core, portable between Ultrascale, Ultrascale+ and Virtex 7 (if it could work with Kintex 7, it would be also nice).
The core must provide SG DMA access for high-speed data transfer, but at the same time should provide the low-bandwidth, but also low-latency to FPGA-implemented control registers via AXI-Lite (control channel).
In the past I've created similar systems for Artix-7 ( https://gitlab.com/WZab/Artix-DMA1 ), however at high data rates I always experienced a problem with starvation of the AXI-Lite channel. The access from the PC to the control register could take as much as a few miliseconds. Probably it has something to do with the PCIe credits system.
I can throttle the data stream, to keep certain bandwidth free for the control channel, but if there are no control commands used, I'd like to be able to use the full bandwidth for data.
Probably the problem should be somehow solved by the appropriate managing of the PCIe credits. I'm quite sure that I'm not the only one who faced that problem. Are there any open solutions available, that solve it?
TIA & Regards,
03-05-2020 06:42 AM
In https://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_4/pg156-ultrascale-pcie-gen3.pdf in Table 2.15 there are ports that allow to monitor the number of credits.
Can I access them in XDMA using the pcie_cfg_mgmt port?
03-05-2020 06:58 AM
In https://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_4/pg156-ultrascale-pcie-gen3.pdf on page 201 there is a description of Configuration Management Interface:
Configuration Management Interface
The ports used by configuration registers are described in Table 2-12, page 28. Root Ports
must use the Configuration Port to set up the Configuration Space. Endpoints can also use
the Configuration Port to read and write; however, care must be taken to avoid adverse
system side effects.
The user application must supply the address as a Dword address, not a byte address.
However, where can I find the addresses of all registers?
03-05-2020 07:14 AM
It seems, that I can access the configuration ports in the pcie3_7x blocks:
However, I don't know how to access them in the XDMA block. I'd like to create a state-machine that would throttle the incoming data when the core runs out of credits.