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Registered: ‎05-20-2018

PCIe DMA subsystem (AXI bridge mode) outstanding issue (ZU19EG)

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We are implementing a PCIe DMA subsystem (AXI-Bridge mode) in ZU19EG device with Vivado 2019.2. We encounter a performance issue, similar to  the report : AR#72747 in xilinx website: https://www.xilinx.com/support/answers/72747.html .  
The AXI outstanding number is set to be 8 (C_S_AXI_NUM_READ = 8), but we found only one AXI read can be issued instead of 8.  Please check "pcie_axis_arvalid" and "pcie_axis_arready" in the attached waveform.  This problem limited our design's performance due to very low data rate in the AXI read channel. Do anyone kown how to increase the outstanding number ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Re: PCIe DMA subsystem (AXI bridge mode) outstanding issue (ZU19EG)

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Could you check if "AXI Slave narow burst support" is enabled or not? If it is, please try by disabling this option. You will find this option in "AXI:MISC" tab in the core configuraiton GUI. 

Thanks.

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Xilinx Employee
Xilinx Employee
245 Views
Registered: ‎08-06-2008

Re: PCIe DMA subsystem (AXI bridge mode) outstanding issue (ZU19EG)

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Could you check if "AXI Slave narow burst support" is enabled or not? If it is, please try by disabling this option. You will find this option in "AXI:MISC" tab in the core configuraiton GUI. 

Thanks.

View solution in original post

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Registered: ‎05-20-2018

Re: PCIe DMA subsystem (AXI bridge mode) outstanding issue (ZU19EG)

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Thanks for your reply!

I am sure "AXI Slave narow burst support" is disabled. 

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Registered: ‎05-20-2018

Re: PCIe DMA subsystem (AXI bridge mode) outstanding issue (ZU19EG)

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The AXI outstanding works after disable ""AXI Slave narow burst". Thanks a lot!

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