01-26-2020 11:11 PM
After designing a successful PCIe DMA system using Xilinx XDMA core, I thought to share a fully extensive guide on how to do it right. I've posted it in Linked. You're welcome to read it:
Part 1: www.linkedin.com/pulse/xilinx-dma-pcie-tutorial-part-1-roy-messinger/
Part 2: www.linkedin.com/pulse/xilinx-dma-pcie-tutorial-part-2-roy-messinger/
Part 3: www.linkedin.com/pulse/xilinx-dma-pcie-tutorial-part-3-roy-messinger/
01-27-2020 07:42 AM
Many thanks for sharing this tutorial. It is indeed a great effort. I am sure many XDMA IP users will find this useful. If you have other tutorials you might have put together, please share those too.
01-28-2020 10:14 AM
I'm reviewing the accuracy of this tutorial by following the steps but finding some inconsistencies. I'm only on creating Block 2 but seeing the comments mention to use axi master bus, but the screenshots show a slave bus. Also in the overall block diagram, there are additional ports (i.e. "cpu_data_bus_rd[31:0]" which are not mentioned in this section.
I'm still going through it so if these issues are resolved later, then you can ignore my comments.
01-28-2020 10:34 AM
Take into account you will need some degree of design level, as I could not give the whole design at such high resolution and explanations. There are alot of do's and don'ts and many guidelines.
Thanks for the comments, though. I will go over it and fix the issues where needed.