10-05-2018 12:17 PM
I am trying to modify the test bench generated by the PCIe DMA core so that I can write to registers in the BAR0 space via the AXI Lite Master that is included in the version of the PCIe DMA core that I have generated. It is a gen2, 4x design targeting an Artix7 device.
The basic test bench is working properly, however I want to test the functionality of the AXI Lite Master by writing and reading control/status registers in the BAR0 space. I have implemented a JESD204B design with two TX and two RX JESD204B cores. This core also contains an AXI Interconnect core which allows a single Master to connect to six slaves. I am just trying to write to some registers located at starting address 32'h00050000 in BAR0 space.
In the pcie_exp_usrapp_tx.v code I created my own task(TSK_DWD_MEM_TEST_DATA_REG) which is a modification of the TSK_MEM_TEST_DATA_BUS task. I have attached the pcie_exp_usrapp_tx.v code along with the sample_test.vh code which contains my call to the TSK_MEM_TEST_DATA_BUS task.
My issue is that I do not see the write on the AXI Lite Master bus. Could you please help? Thanks.
10-11-2018 02:37 PM
How large have you set your BAR0 (AXI Lite) to be? Could it be an index up problem?
Also, have you checked the RP RQ bus at the time of your requests to ensure the address is where you expect?
10-11-2018 06:32 PM
I have set the BAR0 memory space to 4.0 Megabytes.
I am not sure about the second part of your question. I am monitoring the AXI4-Lite Bus from the PCIe DMA core and I never see the writes to the register space. However, I do see the writes/reads to the BAR1 space to configure the PCIe DMA core.
Is there any document that describes the Xilinx Root Port test bench in more detail? There are a lot of files and it is hard to just go through all the code and figure out what is going on.
I am just looking for a little guidance in how to modify the test bench to write to BAR0 space. I will try to attach my xdma core though I usually cannot do it in the tool. Thanks.
10-16-2018 10:17 AM
The Product Guide for the related Integrated Block to your XDMA core will provide more guidance on the test bench. (PG023 for Virtex-7, PG156 for UltraScale, PG213 for UltraScale+).
Also, using those same Product Guides, I would recommend looking at the axis_rq interface on your Root Port model to monitor the outgoing packet address on the Root Port. This should align with the BAR0 address you are seeing. You could also check the axis_cq interface on your endpoint to see if the request packet for BAR0 is showing up there. My guess is that your call of the tasks might be pointing at the wrong BAR indicator, or there might be another issue in the formation of packet.