This query is regarding a custom board which has 4 Banks of DDR connected to PS similar to ZC706.
FPGA is used for Data Acquisition where 4 different types (Gigabit Ethernet, 500MSPS ADC etc) of aperiodic data reaches the FPGA. The data thus fetched has to be sent to a Computer running on Windows 10 over PCIe.
1. Is it possible to configure DMA with four DDR Banks separately via "PCIe/DMA Bridge System for 7-Series" ? If so, What is the procedure ?
2. Is it possible to create an Interrupt request separately for these 4 DDR Banks ? If so, What is the procedure ?
or Will the FIFOs of IP Core forward the data to root-complex without interrupt ?
3. Can a particular C2H Channel be configured for different DDR banks ?
4. How to transfer the Highspeed data acquired from ADCs at PL side to the DDR of PS Side ?