09-13-2018 05:55 AM
I am working on a custom PCIe PCB design, in order to simplify the routing I have changed connection order for the PCIe Lanes to FPGA. On the TX Side, I have reversed the order, but due to the tight design constraints Lane reversal is not easy for the RX Lane and I have routed them like how it shown in the schematic view.
I am in the process of verifying this on the Vivado by synthesis and implement but I would like to get the professional opinion here. I am pretty sure Lanes can be re-order within the code as well but it would be good to understand if it is a concern for the System.
09-13-2018 12:11 PM
09-14-2018 08:19 AM
Thank you for the response, after doing some implementation work on the Vivado I have decided to change the routing so I can exploit x4 lane for the PCIe. I have changed the PCIe RX Lanes into reverse order.
Also looking at the Device GTP Cells, it is possible to reverse the signals but TX and RX has to be on the same GTP Cell.
My understanding is , for example Site X0Y4 must have the TX3 and RX3 or TX2 and RX2 diff pair routed into the site, also PG-054 Page 142 provides information saying there it supports lane reversal for the link partner but also mentions Limited lane reversal capabilities.
So system is not fully flexible to route the RX2 diff pair into the site X0Y4 alongside with TX3