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Visitor
Visitor
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Registered: ‎06-23-2010

PCIe Endpoint Block Plus Example Design

Hi,

I am a newbie for PCIe design, trying to maintain communication between host PC and Hi-tech Global V5 LX330T board via PCIe.

Since the example design did not work directly [the board was not detected by host PC after reboot] I check the clocking between the motherboard and the GTP with logic analyzer.

First of all on the PCIe connector there are 2 pairs of differential clock, but clock exists only at one of them, other pair is blind I guess.

Then this clock from the motherboard goes to jitter attenuator found on the board, and the output is fed to GTP. [shared PMA PLL]

There are switches on the board to adjust the output clock frequency of the jitter attenuator. So I set this to DIV2 (I=>100MHz, O=>250MHz)

Then to be able to figure out what the problem is, I defined GTP_DEBUG in endpoint  verilog source codes, so that I can carry GTPCLK_bufg, REFCLK_OUT_bufg, LINK_UP, cock_lock, pll_lock,  core_clk and user_clk to the logic analyzer output.

 

Now at the logic analyzer I see the following maximum frequencies for the corresponding clocks:

- GTPCLK_bufg : 12.5MHz

- REFCLK_OUT_bufg : 25MHz

- core_clk : between 10MHz and 16.67MHz

- user_clk : between 16.67MHz and 25MHz

 

According to GTP Transceiver User Guide, REFCLK_OUT_bufg is a bypassed clk, generated from CLKIN in Shared PMA PLL

So I assume REFCLK_OUT_bufg should be identical to the jitter attenuator output! But I catch 25MHz here, not 250MHz..

And when I try to connect the attenuator output directly to the logic analyzer output, the design is always unroutable, I can not even use this clock to drive a counter..

 

My assumption is to be able to initiate the communication between the host PC and the board, core_clk must be 250MHz..

 

I stucked at this point and have very short time, so any kind of help would be appreciated.

 

Thanks in advance,

Oguz

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Visitor
Visitor
3,644 Views
Registered: ‎06-23-2010

UPDATE:

 

I realized that regardless of the sys_clk frequency, REFCLK_OUT_bufg is always 25 MHz.

 

Now I connected 50 MHz clock from the board's oscillator to sys_clk and REFCLK_OUT_bufg is again 25 MHz.

 

But of course when I tie sys_clk to ground or VDD, REFCLK_OUT_bufg is constant too.

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