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jyingling
Observer
Observer
181 Views
Registered: ‎07-26-2018

PCIe Endpoint IP not available on Zynq Ultrascale+ XCZU3EG-SFVA625

I am trying to do a POC for a pcie endpoint on a board with the XCZU3EG-SFVA625 part. I'm using Vivado 2020.2. Why is the PCIe IP not available for this part??????

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pvenugo
Moderator
Moderator
115 Views
Registered: ‎07-31-2012

Hi @jyingling ,

XCZU3EG is smaller device and it will not have PCIe block in it.

Please refer to product sheet of ZU+ in Xilinx website to understand more.

 

Regards

Praveen


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barriet
Xilinx Employee
Xilinx Employee
103 Views
Registered: ‎08-13-2007

To be clear, there's generally 2 options for PCIe in MPSoC (or RFSoC):

-the PL-side using GTH (or GTY) and the integrated PCIe bock Gen3x8 in the fabric

-the PS-side Gen2x4 using the GTR and the PS-side PCIe controller... This isn't separate IP - it is part of the PCW configuration.

You don't have the first option here on the smaller ZU3 (with no PL-side PCIe or GTH)

You can find more info on the PS-side PCIe in a few places, e.g.:
-TRM/UG1085 - Chapter 30
-https://www.xilinx.com/support/documentation/application_notes/xapp1289-dma-pcie.pdf (though this is a RP not EP example)
https://www.xilinx.com/Attachment/Xilinx_Answer_71210_PS_PL_PCIe_Drivers_Debug_Guide.pdf

Cheers,
bt

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