04-07-2021 03:39 PM
I am trying to do a POC for a pcie endpoint on a board with the XCZU3EG-SFVA625 part. I'm using Vivado 2020.2. Why is the PCIe IP not available for this part??????
04-12-2021 07:05 AM
Hi @jyingling ,
XCZU3EG is smaller device and it will not have PCIe block in it.
Please refer to product sheet of ZU+ in Xilinx website to understand more.
04-12-2021 07:25 AM
To be clear, there's generally 2 options for PCIe in MPSoC (or RFSoC):
-the PL-side using GTH (or GTY) and the integrated PCIe bock Gen3x8 in the fabric
-the PS-side Gen2x4 using the GTR and the PS-side PCIe controller... This isn't separate IP - it is part of the PCW configuration.
You don't have the first option here on the smaller ZU3 (with no PL-side PCIe or GTH)
You can find more info on the PS-side PCIe in a few places, e.g.:
-TRM/UG1085 - Chapter 30
-https://www.xilinx.com/support/documentation/application_notes/xapp1289-dma-pcie.pdf (though this is a RP not EP example)