cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
santukms
Adventurer
Adventurer
7,411 Views
Registered: ‎09-15-2010

PCIe Endpoint block plus simulation error.........

Jump to solution


Here I have attached all the files obtained from the ISE 12.4 core generator while configuring the endpoint block plus.
Kindly any one from xilinx try simulating these codes and solve the problem of the trn_lnk_up_n being not asserted even
after a very long period after the sys_reset_n being deasserted.I simulated for more than 12 ms with the resolution of simulator being 1ps

 

Reference clock frequency of the endpoint block plus is 100MHz.
X1 lane design obtained from Core generator.I didnt change any option while configuring this IP just choosen verilog language for code generation and device is XC5VSX50T FF1136 speed grade -1 and then clicked generate on the Endpoint block plus GUI.

 

We can see the trn_reset_n being deasserted after sys_reset_n is deasserted but the trn_lnk_up_n is not
being asserted even after very long simulation time in the  waveform attached....

0 Kudos
1 Solution

Accepted Solutions
luisb
Xilinx Employee
Xilinx Employee
9,033 Views
Registered: ‎04-06-2010

I looked at your zip and also your transcript.  I don't see any reference to the Root Port model we provide in the example design.  You need this root partner to link train appropriately.  Otherwise, it will not link train.  You also are not going to be able to loopback the tx to the rx of the endpoint.  An endpoint will not link train to an endpoint.  An endpoint will need a downstream port to link train with.  The Root Port is a downstream port.

 

Hope this helps.

View solution in original post

6 Replies
santukms
Adventurer
Adventurer
7,410 Views
Registered: ‎09-15-2010

 

Here I have attached the transcript message I obtained during SImulation

 

Any one pls reply At the earliest,,,,,,,,,,,,,,,,,,,,,,,,,,

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
9,034 Views
Registered: ‎04-06-2010

I looked at your zip and also your transcript.  I don't see any reference to the Root Port model we provide in the example design.  You need this root partner to link train appropriately.  Otherwise, it will not link train.  You also are not going to be able to loopback the tx to the rx of the endpoint.  An endpoint will not link train to an endpoint.  An endpoint will need a downstream port to link train with.  The Root Port is a downstream port.

 

Hope this helps.

View solution in original post

santukms
Adventurer
Adventurer
7,382 Views
Registered: ‎09-15-2010

Hi

 

Thank you very much for your reply....

 

So now I need to add the codes present in the Simulation folder(dsport,functional...) to the project and then simulate for the proper operation of the endpoint block plus...

 

Am I correct now???

 


0 Kudos
santukms
Adventurer
Adventurer
7,378 Views
Registered: ‎09-15-2010

Hi ,

 

I included the root port model, now the rst_n sinal became deasserted.....

 

 

Thank you a lot for your suggestion....:smileyhappy:

 

I now will analyse the root port model and proceed with it..

once again thank you........

0 Kudos
7,333 Views
Registered: ‎03-04-2011

Hi guys,

 

I am also struggling in simulating the PCIe Endpoint block + my own Tx and Rx Handlers as well.  I am trying to use the Root Port Model provided for simulation as well.....Can you guys give me the instruction/direction in how to do it?

 

Thanks


Chris

0 Kudos
santukms
Adventurer
Adventurer
7,289 Views
Registered: ‎09-15-2010

Hi  ultrasonixhardware ,

 

I added all the codes generated by the coregenerater to my project including the example codes,sources codes and also the codes present in the simulation folder....

 

What kind of error your getting tell me if i know will answer you....

 

thank you,,,,

0 Kudos