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Newbie
Newbie
267 Views
Registered: ‎03-18-2020

PCIe Endpoint

I want to design a simple block design consisting of microblaze processor, ethernet and pcie. Where should I connect the reference clock (refclk) of the AXI Memory mapped to PCIe in my block design? I believe this clock should come from the root complex?

Please help as early as possible!

Thanks!

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

回复: PCIe Endpoint

the reference clock is from an exteral pin which connected to the system clock. It usually comes from the host

you will need to have a IBUFDS to connect to between the pin and the Memory map PCIE.An easiler way is to run the system automation 

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Newbie
Newbie
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Registered: ‎03-18-2020

回复: PCIe Endpoint

Thank you so much! Will try and see how it goes!
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