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Anonymous
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PCIe Fails Timing

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Hello-

  Using a Ultrascale+ XCVU9p-2. Vivado2017.4. I have a very simple design for PCIe DMA. I want to using the AXI-Lite interface to write to the C2H interface on the PCIe DMA. It fails timing badly. 2000+ paths. One path fails pulse. I have a picture of where a majority of the paths fails. Untitled.pngEverything is internal to the PCIe DMA so I don't know how to fix it. Seems like such a simple design should meet timing.

 

pcie.png

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Moderator
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Registered: ‎02-16-2010

I tried one more experiment by keeping all the pinout constraints in your .xdc file as-is and updating the PCIe hard block location to X1Y2 in the XDMA IP GUI. All of the design is now placed in a single SLR. I find there are no timing failures.

design_placement_xdma_2.PNG

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Moderator
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Registered: ‎02-16-2010
If possible, can you share the archive of the project?
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Anonymous
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I tried loading a zip but it was too large. Is there another way you would prefer? Thank you

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Moderator
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Registered: ‎02-16-2010
export the block design to a .tcl file using File --> Export --> Export block design option. Along with this, share the .xdc file of the design.
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Anonymous
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How about the project tcl?

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Moderator
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Registered: ‎02-16-2010
I get the following error when I sourced this .tcl file.
ERROR: [Vivado 12-172] File or Directory '/group/bcapps/venkata/test/forum/HTG_pcie_test/htc_adc_top.v' does not exist
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Anonymous
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here is the block design. It wont let me  attach the xdc unless i change the extension. 

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Anonymous
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Here is the top level verilog. Not much to it.

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Anonymous
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Update. It works on the VCU118. Makes no sense sense when the High Tech Global board uses the same Quads for everything. Any help would be appreciated. I'm not sure how to get it to work when the failures are internal to the core.

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Moderator
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Registered: ‎02-16-2010

I find the timing issue seems related to the design placement. With your design, GT's are placed in one SLR and the logic is placed in a different SLR. Have you selected PCIe location in XDMA GUI based on your hardware requirement?

 design_placement_xdma.PNG

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Moderator
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Registered: ‎02-16-2010

As an experiment, I commented the GT pin constraints in your top-level .xdc file and the refclk constraints. I find the design meet timing. The design is placed fully in a single SLR  in this case.

design_placement_xdma_1.PNG

 

Your .xdc file shows the pins from GT quad 227. So I believe you will need to chose PCIe location as "X1Y2".

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Registered: ‎02-16-2010

I tried one more experiment by keeping all the pinout constraints in your .xdc file as-is and updating the PCIe hard block location to X1Y2 in the XDMA IP GUI. All of the design is now placed in a single SLR. I find there are no timing failures.

design_placement_xdma_2.PNG

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Anonymous
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Hello Venkata. I found the same thing. I assumed my xdc would override the DMA core quad placement. I was wrong. Thank you for your help.

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