PCIe IP configuration

[araquirit]

Hi all,

I'm trying to understand the configuration parameters of the Xilinx PCIe IP and some of the parameters are still not clear to me:

  - Enable Slot Clock Configuration on page 5

  - Pipeline Registers for Transaction Block RAM Buffers on page 10

  - Pipeline for PIPE Interface on page 11

What are the usages of those parameters?

Thank you in advance.

Best regards.

[barryabrown]

 - Enable Slot Clock Configuration

This means that your reference clock comes from the PCIe connector.

PCIe Base Spec 1.1, ch 7.8.7, pg387

Spartan-6 UG654, v3.0, pg56

Barry

[jayer]

For the other two, its choosing if to put pipelining FFs between the Block and MGTs or between the Block and BRAM used to store the incoming and outgoing packets. This is there to make timing easier. If they are checked by default, i would leave them checked. If not and you hae timing issues on those related paths you can try enabling them. Without knowing which core you are using its hard for me to comment on the need.

-john

[araquirit]

Thank you all for your inputs, it helps.