06-17-2019 02:38 PM
I have Xilinx PCIe EP generated using the IP catalog. my design is working well, but once I integrate that piece of design to a subsystem (connecting it to other IPs and using the target's verification environment (maintained by a different team), I get a repeating pring coming from Xilinx protected code:
Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on dix[7:0] followed 0xBB on xil_pcie_3_1_mod155 instance *!*!*!....pcie3_ultrascale_2_i.inst.genblk1.pcie3_uscale_top_inst.pcie3_uscale_wrapper_inst.PCIE_3_1_inst.SIP_PCIE_3_1_INST.BUT.PROTECTED at time 1207000
with each print, the timestamp is increasing in 2nS. meaning 1207000 ... 1209000 ....
it seems like the error is somehow related to the FPGA programming interface which is not part of the PCIe EP RTL, or is at least not easily spotted.
would appreciate any debug assistance, ideas you might have. there are a lot of differences between my own small env/TB where the IP doesn't print that, and the subsystem env/TB where it does. I'm currently onion peeling the differences between the envs, but am not sure I can get to the same level of simulator switches, since the system level env is VERY complicated.
07-10-2019 03:55 PM
Have you searched with the error message in the system level env to know what is triggering the error?
07-11-2019 01:16 PM
The error is originating from the insides of the XILINX IP. I don't know what's directly causing it, but after I removed the Xprop hierarchy, the error stopped showing up. so it has something to do with Xprop.