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Adventurer
Adventurer
230 Views
Registered: ‎10-29-2018

PCIe MGT clock

Dear Sir,

We are designing a PCIe gen 3.0 compliant board using XCZU21DR-FFVD1156-2-E with PCIe x8 configuration. By considering the routing constraint, we have planned to place lane 0 to lane 3 in MGT bank 130 and lane 4 to lane 7 in MGT bank 131. 

can PCIe ref clock be placed in MGT bank 131?

Regards,

Puja

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2 Replies
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Xilinx Employee
Xilinx Employee
162 Views
Registered: ‎06-13-2018

Hi @puja,

In transceiver we can share the MGTREFCLK with neighboring quad please check UG578. Since quad 130 is next to 131 we can share the mgtrefclk. Please create the example design selecting the GT Quad 131 as primary for x8 configuration and trace the sys_clk_gt.  

nmanitri_0-1597034980053.png

 

Regards,

Naveen

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Xilinx Employee
Xilinx Employee
123 Views
Registered: ‎06-13-2018

Hi @puja ,

If i have answered your query, please mark the solution as "Accepted Solution" to close this thread. This may help other customer who face similar issue.

Regards,

Naveen 

 

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