08-09-2020 03:16 AM
We are designing a PCIe gen 3.0 compliant board using XCZU21DR-FFVD1156-2-E with PCIe x8 configuration. By considering the routing constraint, we have planned to place lane 0 to lane 3 in MGT bank 130 and lane 4 to lane 7 in MGT bank 131.
can PCIe ref clock be placed in MGT bank 131?
08-09-2020 09:49 PM
In transceiver we can share the MGTREFCLK with neighboring quad please check UG578. Since quad 130 is next to 131 we can share the mgtrefclk. Please create the example design selecting the GT Quad 131 as primary for x8 configuration and trace the sys_clk_gt.
08-14-2020 10:29 AM