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Visitor eric_ngui
Visitor
427 Views
Registered: ‎04-23-2018

PCIe Maximum payload size

We have XCKU15P inside use a Xilinx PCIE block.

 

At PG213 for the PCIE4 block

when the size of the data block exceeds the maximum payload size configured.

User logic is responsible for splitting the data block into multiple Split Completions when needed(page159)

If we use PG194 for the DMA/Bridge Subsystem for PCI Express in AXI Bridge mode,

Is user logic responsible for splitting the data block into multiple Split Completions

when the size of the data block exceeds the maximum payload size configured,

or  “DMA/Bridge Subsystem for PCI Express in AXI Bridge mode” will take care this by itself.

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1 Reply
Moderator
Moderator
384 Views
Registered: ‎02-16-2010

Re: PCIe Maximum payload size

@eric_ngui

Please check if the following details from PG194 help with your query.

Completion Packets
When the MAX_READ_REQUEST_SIZE is greater than the MAX_PAYLOAD_SIZE, a read
request for PCIe can ask for more data than the master bridge can insert into a single
completion packet. When this situation occurs, multiple completion packets are generated
up to MAX_PAYLOAD_SIZE, with the Read Completion Boundary (RCB) observed.

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