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Visitor pankaj11
Visitor
645 Views
Registered: ‎08-15-2017

PCIe PHY IP with 8bit 250MHz gen1 PIPE interface

Hi ,

Is there a way to generate the Xilinx PCIe PHY with gen1 8-bit PIPE interface?

 

The reason I need this is keep the frequency constant (250MHz in this case) and change only bit-width of PIPE interface to 8b, 16b, 32b and 64b for gen1, 2, 3 and 4 rates respectively.

 

I think this is a general practice followed throughout industry either to keep data-width constant and change frequency or keep frequency constant and change data-width as needed.

 

I am not sure why Xilinx PCIe PHY IP does mix of these two approaches. It will be a great help if you can help me find a way to run gen1 rate at 8bx250M PIPE interface.

 

Thanks in advance for your time and efforts.

-Pankaj

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2 Replies
Moderator
Moderator
602 Views
Registered: ‎02-16-2010

Re: PCIe PHY IP with 8bit 250MHz gen1 PIPE interface

PCIe PHY IP is designed with Xilinx Transceivers (GT) and the IP supports UltraScale/UltraScale+ devices.

With UltraScale/UltraScale+ devices, the minimum interface width supported with GT is 16-bit.
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Visitor pankaj11
Visitor
584 Views
Registered: ‎08-15-2017

Re: PCIe PHY IP with 8bit 250MHz gen1 PIPE interface

Thanks Venkata for the quick response.

 

But to make the IP compatible with other PCIe controllers in industry, can Xilinx team change this IP to support constant frequency and variable bitwidth only operation in future?

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