03-22-2017 03:53 AM
PCIe PHY Ultrascale Documentation pg239 - clocking
Hi I am working with the XCVU440 Ultrascale device. I am reading PG239 PCI Express PHY v1.0 docuemntation that describes the ultrascale PCIe PHY / PIPE.
ON page 23 there is a section on clocking.
Please could someone explain the difference between coreclk and userclock.
I am doing an ASIC FGA emulation project and our PCIe MAC ( PCIe core excluding the PIPE/PHY ) requires a clock for PIPE data path ( PCLK ) also the core requires a clock for other processes. Should I use userclk or coreclk.
I note coreclk is 250MHz in my example.