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Adventurer
Adventurer
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Registered: ‎02-08-2016

PCIe PHY Ultrascale Documentation pg239 - clocking

PCIe PHY Ultrascale Documentation pg239 - clocking

 

Hi I am working with the XCVU440 Ultrascale device. I am reading PG239 PCI Express PHY v1.0 docuemntation that describes the ultrascale PCIe PHY / PIPE.

 

ON page 23 there is a section on clocking.

 

Please could someone explain the difference between coreclk and userclock.

I am doing an ASIC FGA emulation project and our PCIe MAC ( PCIe core excluding the PIPE/PHY ) requires a clock for PIPE data path ( PCLK ) also the core requires a clock for other processes. Should I use userclk or coreclk.

 

I note coreclk is 250MHz in my example.

 

Thanks SImon

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Observer
Observer
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Registered: ‎09-15-2012

For PIPE interface clock is 250MHz when the link is operating at 5 GT/s and 125MHz when operating at 2.5 GT/s.

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Adventurer
Adventurer
2,515 Views
Registered: ‎02-08-2016

Thanks for this information!
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