cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
3,503 Views
Registered: ‎09-12-2010

PCIe PLB bridge - Address translation table setting

Dear Xilinx developers.

I have a problem of using bridge for PCIE.

Eventhough I was chaged IPIFBAR2PCIBAR_0n value (such as 0x0000_000e or 0xe000_0000),

I can't see changeed data from bram of bridge.  (I don't know that how to device can see the any memory area of hose DRAM)

 

Initailly, I can see the data  at  fbbf_XXXX in host side.

Also I can see the data at FFFF_XXXX in device side.

both data in host and device changed by synchronized.

 

and then I trying to changhe the  C_IPIFBAR2PCIBAR_0 value

I expect that I can see the different data from not assignd area from host side(0xfbbf_0000)

But I can see new data.

 

Please check our mhs. setting value.

If you have the sample with address translation on the Bridge for PCIe, please share to me.

 

Best regards

JW LEE

 

p.s Now I used the FX200T core FPGA.(PLDA, XprsssGen2-V5) 

 

 

 

 


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 12.2 Build EDK_MS2.63c
# Tue Sep 07 15:17:05 2010
# Target Board:  Xilinx Virtex 5 ML507 Evaluation Platform Rev A
# Family:    virtex5
# Device:    xc5vfx70t
# Package:   ff1136
# Speed Grade:  -1
# Processor number: 1
# Processor 1: ppc440_0
# Processor clock frequency: 400.0
# Bus clock frequency: 100.0
# Debug Interface: FPGA JTAG
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I, VEC = [3:0]
 PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I, VEC = [3:0]
 PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK
 PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK


BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 PARAMETER C_SPLB0_USE_MPLB_ADDR = 1
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000
 PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC440CLK = clk_400_0000MHzPLL0
 PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
 PORT CPMMCCLK = clk_100_0000MHzPLL0_ADJUST
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_0
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_100_0000MHzPLL0_ADJUST
 PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
 PARAMETER C_SPLB_P2P = 0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xffff0000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
END

BEGIN plbv46_pcie
 PARAMETER INSTANCE = PCIe_Bridge
 PARAMETER C_IPIFBAR_NUM = 1
 PARAMETER C_PCIBAR_NUM = 1
 PARAMETER C_DEVICE_ID = 0x1100
 PARAMETER C_VENDOR_ID = 0x1556
 PARAMETER C_CLASS_CODE = 0x040000
 PARAMETER C_REV_ID = 0x00
 PARAMETER C_SUBSYSTEM_ID = 0x1100
 PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x1556
 PARAMETER C_COMP_TIMEOUT = 1
 PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000
 PARAMETER C_PCIBAR2IPIFBAR_0 = 0xffff0000
 PARAMETER C_PCIBAR_LEN_0 = 16
 PARAMETER C_BOARD = none
 PARAMETER HW_VER = 4.04.a
 PARAMETER C_BASEADDR = 0x85c00000
 PARAMETER C_HIGHADDR = 0x85c0ffff
 PARAMETER C_IPIFBAR_0 = 0xc0000000
 PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff
 PARAMETER C_INCLUDE_BAROFFSET_REG = 1
 PARAMETER C_PCIBAR_AS = 0
 PARAMETER C_NO_OF_LANES = 4
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE MPLB = plb_v46_0
 PORT REFCLK = clk_100_0000MHzPLL0_ADJUST
 PORT RXN = fpga_0_PCIe_Bridge_RXN_pin
 PORT RXP = fpga_0_PCIe_Bridge_RXP_pin
 PORT TXN = fpga_0_PCIe_Bridge_TXN_pin
 PORT TXP = fpga_0_PCIe_Bridge_TXP_pin
 PORT IP2INTC_Irpt = PCIe_Bridge_IP2INTC_Irpt
 PORT MSI_request = net_gnd
END

BEGIN xps_central_dma
 PARAMETER INSTANCE = xps_central_dma_1
 PARAMETER HW_VER = 2.02.a
 PARAMETER C_BASEADDR = 0x80200000
 PARAMETER C_HIGHADDR = 0x8020ffff
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE SPLB = plb_v46_0
 PORT IP2INTC_Irpt = xps_central_dma_1_IP2INTC_Irpt
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 400000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = PLL0
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 4.00.a
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_100_0000MHzPLL0_ADJUST
 PORT CLKOUT1 = clk_200_0000MHzPLL0
 PORT CLKOUT2 = clk_400_0000MHzPLL0
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_inst
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = clk_100_0000MHzPLL0_ADJUST
 PORT Ext_Reset_In = sys_rst_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Intr = PCIe_Bridge_IP2INTC_Irpt & xps_central_dma_1_IP2INTC_Irpt
 PORT Irq = ppc440_0_EICC440EXTIRQ
END

 

 

0 Kudos
Reply
1 Reply
Highlighted
Explorer
Explorer
3,477 Views
Registered: ‎10-01-2008

Hi,

 

I am not Xilinx developer. But since it looks like you are using the ML507 board based on your MHS file, there is a working PLB PCIe design provided in this application note. Would this help you?

 

XAPP1040 - Reference System: PLBv46 Endpoint Bridge for PCI Express in a ML507 Embedded Development Platform: https://secure.xilinx.com/webreg/clickthrough.do?cid=113623&license=RefDesLicense

 

-Yan Shun Li

0 Kudos
Reply