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Registered: ‎04-02-2008

PCIe RCB in the End Point



I have a design where we use the Xilinx Blockplus EP in the x4 configuration. Here.. the Max Payload is set to 256 bytes/TLP. In the code, we check for the RCB from RC and based on that we force the application logic to request MWr/MRd in 64-byte TLPs.. such that we do not cross the RCB. But wont this put a bottleneck on the PCIe throughput?


In our simulations we're trying to sent varying payload sizes.. from 4 bytes to 1K/2K.. but due to this 64-byte limitation..the EP always requests MWr or MRds in 64b TLPs only for payloads above 64bytes.. ie completions are always 64bytes. So when a 1 K data has to be sent it splits this up to multiple 64-byte completions.. Won't this reduce the effective throughput of the PCIe link...


Is it possible to increase the completion (RCB)  to that of the max payload (256)? What are the issues that will be faced if we increase the completion size to 256bytes?




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