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mansuramin
Adventurer
Adventurer
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Registered: ‎12-04-2019

PCIe V1.3 write first collision advisroy

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Hello 

How can I change the read and write operation to the ram that is autogenerated by the PCIe IP? I dont see an option in the IP config window to set the operation as READ_FIRST, NO_CHANGE, WRITE_FIRST. It seems to be selected automatically. 

I am seeing this warning after I compile and build my design with PCIe. 

I am using Vivado 2018.2 and PCIe v1.3 avaiable in the IP catalog. 

REQP-1858#10 Advisory
RAMB36E2_writefirst_collision_advisory
Synchronous clocking is detected for BRAM (u_pcie_example_project/pcie4_uscale_plus_0_i/inst/pcie_4_0_pipe_inst/pcie_4_0_bram_inst/RAM32K.bram_comp_inst/bram_16k_1_int/ECC_RAM.RAMB36E2[3].ramb36e2_inst) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
Related violations: <none>

 

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garethc
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Registered: ‎06-29-2011

Hi @mansuramin 

This is not something that is PCIe specific and you cannot change with the PCIe IP. It is an attribute of the RAMB36E2 BRAM that is used with the PCIe example design. You can refer to UG573, UltraScale Architecture Memory Resources User Guide for more information on the Block RAM Resources. From Page 39 the Block RAM attributes are detailed in Table 1-16 and you can see the WRITE_MODE_A and WRITE_MODE_B attributes listed.

Note that this is only a warning that can more than likely be ignored so why are you loooking into this? Are you seeing issues?

Thanks,

Gareth


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garethc
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Registered: ‎06-29-2011

Hi @mansuramin 

This is not something that is PCIe specific and you cannot change with the PCIe IP. It is an attribute of the RAMB36E2 BRAM that is used with the PCIe example design. You can refer to UG573, UltraScale Architecture Memory Resources User Guide for more information on the Block RAM Resources. From Page 39 the Block RAM attributes are detailed in Table 1-16 and you can see the WRITE_MODE_A and WRITE_MODE_B attributes listed.

Note that this is only a warning that can more than likely be ignored so why are you loooking into this? Are you seeing issues?

Thanks,

Gareth


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