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tony_tse
Visitor
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Registered: ‎01-06-2021

PCIe X4 Linkwidth not reliably negotiated with K7325T and Motherboard

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Hello,Everyone,

When we connect a Board(based on K7325T-2FFG900) to a motherboard via PCI express ,We see that the link width is not always X8 as desired,But X2 sometimes,

When I check cfg_lstatus(9:4) in PCIe IP Core, I see that value is 000010,it shoud be 001000.

We produced several hundreds the board every year,and the type of the board has been used on more than 100 machines,it work well ,So I think the design is ok .,So how can I check and fix the error ? Thank you.

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nmanitri
Xilinx Employee
Xilinx Employee
193 Views
Registered: ‎06-13-2018

Hi @tony_tse ,

You need to check the termination resistor. Is correctly added in the board or NOT? 
Please refer PCB user guide for better understanding.

https://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

Regrads,

Naveen 

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tony_tse
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Registered: ‎01-06-2021

sorry, it should be PCIeX8 Linkwidth not reliaby negotiated..,not PCIeX4.

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nmanitri
Xilinx Employee
Xilinx Employee
347 Views
Registered: ‎06-13-2018

Hi @tony_tse ,

What is the failure rate? You have mention that you have several boards running in the production. From how long these boards are in production? 

Can you create our example design and check are you able to replicate the issue?

Which Vivado version you are using? 

Where LTSSM is getting stuck? You can enabled the "JTAG Debugger" within the Tab "Add. Debug Options." This will add in a hw_axi_1 module to the design that shows you the LTSSM data. We document in https://www.xilinx.com/support/documentation/ip_documentation/pcie_7x/v3_3/pg054-7series-pcie.pdf#page=242 how to get the results in HW.

Thanks,

Naveen

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tony_tse
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Registered: ‎01-06-2021

hello,nmanitri,

 Thanks for your reply.the boards have worked well in our production for 5-6years.But from last year, some new boards have this problem,maybe 40-50 boards in 100pcs have this problem.so i guess if something with the FPGA.

I use ISE14.7,and when i create IP using vivado2020.1,the result is the same .

I try to isolate the upper lanes and then force the link to attemp to train as an x1 or x4(by placing scotch tape on the upper lane pins on the connector),the result is always right.PCIe_1.pngPCIE_2.png

In AR56616, it said that the issue was resolved by adding a resistor on the board trace that allowed the RP to correctly detect receiver on all lanes(page57-58),but don't point out how to add the resistor,So,Can you tell me ? Thank you.

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nmanitri
Xilinx Employee
Xilinx Employee
194 Views
Registered: ‎06-13-2018

Hi @tony_tse ,

You need to check the termination resistor. Is correctly added in the board or NOT? 
Please refer PCB user guide for better understanding.

https://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

Regrads,

Naveen 

View solution in original post

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