10-21-2020 01:07 PM
So far I am unable go get an example design of the pcie_xdma block up and running. The cfg_ltssm_state is cycling between 0 -> 1 -> 2 ->0.
Simulators Tried: Vivado, Questa 10.7c, Questa 2019.3
Target: Kintex UltraScale xcku060-ffval517-2-e
I have include a screen shot of the waves, and also the project tcl script. Has anyone else run into this issue before?
11-02-2020 09:35 PM
Please confirm did you modify the example design? Because i am NOT able to replicate this issue.
From your LTSSM it seems that from Polling.Active state it is moving to the Detect state.
This happens, if no TS1 and TS2 ordered-Sets are received with the Link and lane number field set to the PAD symbol on any lane.
Can you please check with Gen1? Is Gen1 is working fine for you?
11-03-2020 09:08 AM
Thank you for the answer guide, I was not aware of one that supported Ultrascale, that will be helpful. I did not modify the example design, I simply right clicked on the block in my design and clicked on "Open IP Example Design". This opened a new project in Vivado 2019.1. When running the Vivado, or Questa simulation generated by this project I was getting the results above. I am curious to know if you tried to use my project .tcl script to try and recreate the project and the problem?
I would like to spend more time helping to figure this out, but I have already spend a considerable amount of time with no success, and I ended up going to a 3rd party model where the link training worked right out of the box.
11-03-2020 09:30 AM
Thank you for your quick reply.
Please share your xci file. I will try at my end with your configuration.
Also, did you get chance to check this issue in Vivado 2020.1 or in Vivado 2019.2?