12-18-2018 12:57 AM
I'm using PCIe XDMA on artix7.
How to configure the size (memory space) of the PCIe to DMA interface? now it is allwase 64K
in my case to change the size of BAR1 because the PCIe to AXI LITE is enabled.
I need a simple and straightforward answer.
12-19-2018 09:08 AM
PCIe to DMA BAR1 is used for accessing the DMA register space. So it has a fixed space of 64K.
If you are referring to the BAR "PCIe to Master AXI-Lite", this BAR size can be expanded when you enable it in the GUI. Enabling this BAR does not impact the size of PCIe to DMA BAR1.
12-20-2018 01:09 AM
Im a bit confue now, which AXI port I should connect to a DDR ?
My DDR size is 2G
if the size is 64K then it is not good for the DDR BAR ?
DO I need to configure the DDR space size from the host?
what if i dont add the AXI_Lite port?
which port goes to the memory??
I used the example from:
but for artix 7 EVM
12-20-2018 09:43 AM
You have to connect the DDR to M_AXI port of the DMA IP. With DMA IP, the data transfer is taken care by the DMA engine. The data read/write operation from/to DDR is not a BAR hit through a memory read/write from the host. It is an AXI transaction initiated by the DMA engine. So there is no BAR assignment for the slave connected to M_AXI port of the XDMA IP.
12-22-2018 11:31 PM
If there is no BAR assignment for the slave connected to M_AXI port of the XDMA IP, How does the host know how mach memory to alocate fo the DDR?
How dose the host know the DDR MM address?
01-04-2019 03:29 PM
Host does not allocate memory for the DDR. The memory for DDR is allocated in the AXI address space.
I would recommend reading PG195 to understand the DMA transfer process. Basically, Driver sets descriptors in host memory which contains source and destination address for the transfer. For H2C transfer (Host to Card), I believe the driver designer needs to know the AXI address to which the DDR is mapped to. This helps him to set the destination address in the descriptor to have the correct location.