08-04-2020 01:45 AM - edited 08-04-2020 05:21 AM
Vivado Version: 2020.1
Device Family : kintex7 on KC705.
Name of the IP: DMA/Bridge Subsystem for PCI Express - DMA mode - Configured as following
- PCIe Gen2 x4, AXI Data Width 64
- PCIe to DMA (64-bit Enable, Prefetable),
- PCIe to DMA Bypass (64-bit Enable, Size 2GB
Hello Xilinx community,
I am facing an issue when issuing 64-bit Read Write Access on AXI Bypass interface on our KC705 development board
We have executed the same SW Application on "DMA/Bridge Subsystem for PCI Express - DMA mode" on Virtex7 Ultrascale in PCIe Gen3 Mode and no bug have been found.
Can you please confirm there is a problem and if yes, is there anyway to solve it?
08-13-2020 02:30 AM
try 1MB address space on the DMA bypass.
I had also problems when I use 64bit enabled and another address space than 1MB.
Without 64bit, I checked address spaces from 256kB to 16MB, all was fine.
The return value 0xFFFF... is a errornous AXI access.
Perhaps it helps. Good luck
08-13-2020 02:53 AM
Thanks for the feedback but unfortunatly I need this 2-GB memory space on DMA Bypass and 64-bit enable on KC705.
I don't have any problem on Virtex7 Ultrascale though with 128-GB memory space.... which is quiete odd.
The only solution I have found so far is to use the "AXI Memory Mapped to PCie" Endpoint interconnected with CDMA for KC705.