cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
ndnsoulja
Participant
Participant
1,728 Views
Registered: ‎10-24-2018

PCIe XDMA - how do i change the Masters connected to AXI-Lite using AXI-Interconnect

How do I write to the different Masters from AXI-Interconnect? I have the AXI-Lite attached to AXI-Interconnect which has 2 Masters. The tool auto assigned the addresses shown in the "Address editor" screenshot. How do I write to M01_AXI (address 0x44a1_0000)?

 

I'm able to see my commands I write to /dev/xdma0_user using ./reg_rw program from Xilinx.  For example when I do, I get the below result along with the given screenshots from the terminal and ILA. As you can see the AWADDR is 0x44a00000... 

 ./reg_rw /dev/xdma0_user 0x0 w 0x1
[root@localhost tools]# ./reg_rw /dev/xdma0_user 0x0 w 0x1
argc = 5
device: /dev/xdma0_user
address: 0x00000000
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7fb6a617f000.
Write 32-bits value 0x00000001 to 0x00000000 (0x0x7fb6a617f000)
[root@localhost tools]#

 

block diagramblock diagramaddress editoraddress editorerror at 0x44aerror at 0x44aaxilite write at 0x0axilite write at 0x0ila results axilite write at 0x0ila results axilite write at 0x0

0 Kudos
24 Replies
ndnsoulja
Participant
Participant
1,649 Views
Registered: ‎10-24-2018

Hello? any help would be appreciated.
0 Kudos
venkata
Moderator
Moderator
1,641 Views
Registered: ‎02-16-2010

Hi @ndnsoulja 

The command to use for accessing M_AXI is below. 

./reg_rw /dev/xdma0_user 0x1_0000 w 0x1

For this command to be successful, following are required.

1. The DMA to M_AXILIte BAR size setting with the XDMA IP should be greater than 128K, which is the total allocated AXI address space based on the address editor settings. You can check this in IP GUI.

2. Root port should have enumerated at least 128K size of BAR for DMA to M_AXILte BAR. You can check this by running the command -- "lspci -vvv -d <device_id>:" -- ex: lspci -vvv -d 10ee: --> in this example 10ee is the device ID. 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
ndnsoulja
Participant
Participant
1,637 Views
Registered: ‎10-24-2018

hi @venkata , This is the setting I have in the DMA IP.

 

image.png

0 Kudos
ndnsoulja
Participant
Participant
1,630 Views
Registered: ‎10-24-2018

hi @venkata , If i do any write above 0xBFFF I get the same "segmented" error as above. with the settings above. Please help

0 Kudos
venkata
Moderator
Moderator
1,607 Views
Registered: ‎02-16-2010

Hi @ndnsoulja 

What do find with lspci command? 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
ndnsoulja
Participant
Participant
1,589 Views
Registered: ‎10-24-2018

@venkata see below screenshots. I'm trying to write to the "slot 3" in the ILA screenshot, which is connected to M01_AXI of the interconnected and offset address of 0x44A1_0000 in Address Editor. But ILA is only writing to Slot 0. 

image.png

 

01:00.0 Serial controller: Xilinx Corporation Device 903f (prog-if 01 [16450])
        Subsystem: Xilinx Corporation Device 0007
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Step         ping- SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-          <MAbort- >SERR- <PERR- INTx-
        Latency: 0
        Interrupt: pin A routed to IRQ 16
        Region 0: Memory at df000000 (32-bit, non-prefetchable) [size=1M]
        Region 1: Memory at df100000 (32-bit, non-prefetchable) [size=64K]
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot         -,D3cold-)
                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [70] Express (v2) Endpoint, MSI 00
                DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <64ns, L         1 <1us
                        ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowe         rLimit 75.000W
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupporte         d-
                        RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 256 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPe         nd-
                LnkCap: Port #0, Speed 8GT/s, Width x16, ASPM not supported, Exi         t Latency L0s unlimited, L1 unlimited
                        ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 8GT/s, Width x16, TrErr- Train- SlotClk+ DLActive-          BWMgmt- ABWMgmt-
                DevCap2: Completion Timeout: Range BC, TimeoutDis+, LTR-, OBFF N         ot Supported
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OB         FF Disabled
                LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
                         Transmit Margin: Normal Operating Range, EnterModifiedC         ompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+,          EqualizationPhase1+
                         EqualizationPhase2+, EqualizationPhase3+, LinkEqualizat         ionRequest-
        Capabilities: [100 v1] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-          MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-          MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+          MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
        Capabilities: [1c0 v1] #19
        Kernel driver in use: xdma
        Kernel modules: xdma

 

image.png

 

 

[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x1_0000 w 1
argc = 5
device: /dev/xdma0_user
address: 0x00000001
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f8253743000.
Write 32-bits value 0x00000001 to 0x00000001 (0x0x7f8253743001)

 

 
 

outputoutput

0 Kudos
ndnsoulja
Participant
Participant
1,577 Views
Registered: ‎10-24-2018

hi @venkata using the format you suggested above:

 

./reg_rw /dev/xdma0_user 0x1_0000 W 0x1

 

 returns

 

[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x1_0000 W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x00000001
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7fd6159a2000.
Write 32-bits value 0x00000001 to 0x00000001 (0x0x7fd6159a2001)

 

why is the Address 0x00000001?

 

0 Kudos
venkata
Moderator
Moderator
1,557 Views
Registered: ‎02-16-2010

Hi @ndnsoulja 

Based on the log below, I wonder if the offset "0x1_0000" is considered as "0x1". 

 

[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x1_0000 w 1
argc = 5
device: /dev/xdma0_user
address: 0x00000001
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f8253743000.
Write 32-bits value 0x00000001 to 0x00000001 (0x0x7f8253743001)

 

Can you try the command below?

 

./reg_rw /dev/xdma0_user 0x10000 w 1

 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
ndnsoulja
Participant
Participant
1,531 Views
Registered: ‎10-24-2018

hi @venkata this is the result I got. i also attached some other values I tried. All only trigger SLot 0 in the chipscope. 

[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x10000 W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x00010000
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f09a8cad000.
Write 32-bits value 0x00000001 to 0x00010000 (0x0x7f09a8cbd000)
Segmentation fault (core dumped)

 

[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0xf W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x0000000f
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7fe65a6dc000.
Write 32-bits value 0x00000001 to 0x0000000f (0x0x7fe65a6dc00f)
[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x1f W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x0000001f
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f93895e0000.
Write 32-bits value 0x00000001 to 0x0000001f (0x0x7f93895e001f)
[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0xfff W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x00000fff
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7fbd4bdf2000.
Write 32-bits value 0x00000001 to 0x00000fff (0x0x7fbd4bdf2fff)
[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0xafff W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x0000afff
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f691258b000.
Write 32-bits value 0x00000001 to 0x0000afff (0x0x7f6912595fff)
Segmentation fault (core dumped)
[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x1fff W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x00001fff
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f210378e000.
Write 32-bits value 0x00000001 to 0x00001fff (0x0x7f210378ffff)
[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x00001fff W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x00001fff
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f184382e000.
Write 32-bits value 0x00000001 to 0x00001fff (0x0x7f184382ffff)
[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x00002fff W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x00002fff
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f5c3b27c000.
Write 32-bits value 0x00000001 to 0x00002fff (0x0x7f5c3b27efff)
[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x0000bfff W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x0000bfff
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7fed01644000.
Write 32-bits value 0x00000001 to 0x0000bfff (0x0x7fed0164ffff)
[root@localhost tools]#  ./reg_rw /dev/xdma0_user 0x0000cfff W 0x1
argc = 5
device: /dev/xdma0_user
address: 0x0000cfff
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f7ebf56c000.
Write 32-bits value 0x00000001 to 0x0000cfff (0x0x7f7ebf578fff)
Segmentation fault (core dumped)
​

 

0 Kudos
ndnsoulja
Participant
Participant
1,524 Views
Registered: ‎10-24-2018

hi @venkata 

here's some more information: I placed an ILA on the input to the interconnect and seeing that in the SLOT 2: 

 

image.png./reg_rw /dev/xdma0_user 0x2_0000 W 0x0./reg_rw /dev/xdma0_user 0x2_0000 W 0x0./reg_rw /dev/xdma0_user 0x44a1_0000 W 0x0./reg_rw /dev/xdma0_user 0x44a1_0000 W 0x0./reg_rw /dev/xdma0_user 0x0001_0000 W 0x0./reg_rw /dev/xdma0_user 0x0001_0000 W 0x0

 

[root@localhost tools]# ./reg_rw /dev/xdma0_user 0x00010000 W 0x0
argc = 5
device: /dev/xdma0_user
address: 0x00010000
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f9ddbfcf000.
Write 32-bits value 0x00000000 to 0x00010000 (0x0x7f9ddbfdf000)
Segmentation fault (core dumped)

Do i need to change these setting?

xdma  propertiesxdma properties

 

0 Kudos
venkata
Moderator
Moderator
1,456 Views
Registered: ‎02-16-2010

Can you share the capture on slot_2 with the following command?

./reg_rw /dev/xdma0_user 0x00010000 W 0x0

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
ndnsoulja
Participant
Participant
1,454 Views
Registered: ‎10-24-2018

I pasted it above, but here it is again. That command doesn't trigger anything and give the below error:

[root@localhost tools]# ./reg_rw /dev/xdma0_user 0x00010000 W 0x0
argc = 5
device: /dev/xdma0_user
address: 0x00010000
access type: write
access width given.
access width: word (32-bits)
character device /dev/xdma0_user opened.
Memory mapped at address 0x7f9ddbfcf000.
Write 32-bits value 0x00000000 to 0x00010000 (0x0x7f9ddbfdf000)
Segmentation fault (core dumped)
0 Kudos
mattwaltz
Adventurer
Adventurer
1,448 Views
Registered: ‎06-05-2017

The correct way to do this is to set the PCIe BAR to allow access to all the masters you need using the BAR size.

For instance, I would do this in the configuration for the IP Block:

PCIe BAR Base Address: 0x40000000

PCIe BAR Size: 1MiB

This will then allow you to access everything from 0x40000000 + 1MiB across the PCIe BAR. Therefore, map your AXI peripherals in accordingly to fit in this region.

0 Kudos
ndnsoulja
Participant
Participant
1,442 Views
Registered: ‎10-24-2018

Hi @mattwaltz I tried this setting: 

but that didn't seem to work. Are these the setting you're talking about?

xdma propertiesxdma properties

0 Kudos
mattwaltz
Adventurer
Adventurer
1,439 Views
Registered: ‎06-05-2017

No, not those settings. Double click on the PCIe Block Design IP and change the settings there. You need to set the base address to 0x40000000, size to 1MiB, and then map your slaves into that region of memory. From the host perspective, the base address is zero, so if your slave is at address 0x40001000, then the host would see that as address 0x00001000.

0 Kudos
ndnsoulja
Participant
Participant
1,431 Views
Registered: ‎10-24-2018

Hi @mattwaltz thanks for your help! the address editor automatically sets these to the below. is that offset address wrong to use? 

image.pngimage.png

0 Kudos
ndnsoulja
Participant
Participant
1,424 Views
Registered: ‎10-24-2018

Hi @venkata could you talk to your colleagues to see if they know? I've spent too much time just trying to figure this issue out. 

this is the output from dmesg i'm seeing hoping this gives you some more insight:

[  764.521749] xdma:cdev_xvc_init: xcdev 0xffff8ae6ab8d9958, bar 0, offset 0x40000.
[  800.263896] xdma:remove_one: pdev 0xffff8ae6ad15f000, xdev 0xffff8ae6ab8d8000, 0xffff8ae3206f6000.
[  800.263899] xdma:xpdev_free: xpdev 0xffff8ae6ab8d8000, destroy_interfaces, xdev 0xffff8ae3206f6000.
[  800.268973] xdma:xpdev_free: xpdev 0xffff8ae6ab8d8000, xdev 0xffff8ae3206f6000 xdma_device_close.
[  820.391465] xdma:xdma_mod_init: Xilinx XDMA Reference Driver xdma v2019.2.51
[  820.391469] xdma:xdma_mod_init: desc_blen_max: 0xfffffff/268435455, sgdma_timeout: 10 sec.
[  820.391489] xdma:xdma_threads_create: xdma_threads_create
[  820.391795] xdma:xdma_device_open: xdma device 0000:01:00.0, 0xffff8ae6ad15f000.
[  820.391899] xdma:map_single_bar: BAR0 at 0xdf000000 mapped at 0xffffa0fb82000000, length=1048576(/1048576)
[  820.391905] xdma:map_single_bar: BAR1 at 0xdf100000 mapped at 0xffffa0fb81c60000, length=65536(/65536)
[  820.391907] xdma:map_bars: config bar 1, pos 1.
[  820.391909] xdma:identify_bars: 2 BARs: config 1, user 0, bypass -1.
[  820.391943] xdma:probe_one: 0000:01:00.0 xdma0, pdev 0xffff8ae6ad15f000, xdev 0xffff8ae68ff2a000, 0xffff8ae68ff2c000, usr 16, ch 1,1.
[  820.393406] xdma:cdev_xvc_init: xcdev 0xffff8ae68ff2b958, bar 0, offset 0x40000.
[ 1057.841030] reg_rw[10492]: segfault at 7f4e10efb000 ip 0000000000400dc2 sp 00007fff0d9accf0 error 6 in reg_rw[400000+2000]
[ 1107.833493] reg_rw[10546]: segfault at 7fd8ad443fff ip 0000000000400dc2 sp 00007ffe67e67ea0 error 6 in reg_rw[400000+2000]
[ 1173.075660] reg_rw[10613]: segfault at 7fdc35f90001 ip 0000000000400dc2 sp 00007ffd15b58140 error 6 in reg_rw[400000+2000]
[ 1186.959785] reg_rw[10629]: segfault at 7f5b3a467001 ip 0000000000400dc2 sp 00007ffe388383c0 error 6 in reg_rw[400000+2000]
[ 1507.233938] reg_rw[10951]: segfault at 7f3d13832ff1 ip 0000000000400dc2 sp 00007ffe98c83080 error 6 in reg_rw[400000+2000]
[ 3691.846539] reg_rw[13072]: segfault at 7feddefc3fff ip 0000000000400dc2 sp 00007ffeb4391e20 error 6 in reg_rw[400000+2000]
0 Kudos
venkata
Moderator
Moderator
1,398 Views
Registered: ‎02-16-2010

Hi @ndnsoulja 

The address editor settings can be manually updated. It is not required to keep the auto generated address map settings. 

When you try the command below, whether slot_2 is also is not getting triggered? Let me know the result when you match the "PCIe to AXI translation" setting to the base address of S00_AXI.

./reg_rw /dev/xdma0_user 0x00010000 W 0x0

 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
ndnsoulja
Participant
Participant
1,386 Views
Registered: ‎10-24-2018

@venkata 

Correct when doing that command nothing gets triggered and i get the "segmention fault (core dumped)" in the host side.

I originally set the PCIe to Axi translation to 0x44A00000 and that matched what was in the slaves S00 - 0x44A0_0000, and 0x44A1_0000. image.pngimage.png

0 Kudos
ndnsoulja
Participant
Participant
1,279 Views
Registered: ‎10-24-2018

@venkata I've attached my block diagram for your consideration and hope you can look at it. 

Please help as this is a time sensitive issue now. 

0 Kudos
ndnsoulja
Participant
Participant
1,264 Views
Registered: ‎10-24-2018

@venkata @mattwaltz 

Hi guys, looking at "reg_rw.c" I notice this 

Line 42: #define MAP_SIZE (32*1024UL)
Line 43: #define MAP_MASK (MAP_SIZE - 1)
Line 100: 	map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
Line 195: 	if (munmap(map_base, MAP_SIZE) == -1)

but if i change MAP_SIZE to below:

Line 42: #define MAP_SIZE (128*1024UL)
Line 43: #define MAP_MASK (MAP_SIZE - 1)
Line 100: 	map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
Line 195: 	if (munmap(map_base, MAP_SIZE) == -1)

 I'm not getting the "Segmentation fault (core dumped)" anymore and I can see the ILAs writing to address 0x44a10000. 

Are there any issues changing this would cause down to line?

./reg_rw /dev/xdma0_user 0x10000 w 0x0000./reg_rw /dev/xdma0_user 0x10000 w 0x0000image.png

0 Kudos
venkata
Moderator
Moderator
1,256 Views
Registered: ‎02-16-2010

Hi @ndnsoulja 

I believe the update should be fine. You are increasing the size of the virtual address space allocated with reg_rw.c application. 

Please refer to the link below for explanation of "mmap" used to allocate the virtual address space. 

http://man7.org/linux/man-pages/man2/mmap.2.html

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
isz-sil
Observer
Observer
1,059 Views
Registered: ‎06-12-2019

This issue is hunting me as well....

 

I have to control several Axi slaves by the Axi Lite Master port of the XDMA. I did the same as you, hooked an axi interconnect between the XDMA Axi Lite M and the other Axi Light S IPs. But it looks when I have more then 16 bits of address assigned to those slaves, I just simply got the segmentation fault when I try to read/write from those addresses.

 

Would be nice some more explanation from Xilinx on that.

 

Thanks!

/Is

0 Kudos
ndnsoulja
Participant
Participant
1,040 Views
Registered: ‎10-24-2018

did you try the solution above?

after you make the changes to rw_reg.c and save, you have to run "make" 

0 Kudos