02-04-2020 08:12 PM
My concerns are as following
1. I want to implement a ZCU102 (A) as endpoint where it will recieve data from a root ZCU102(B) over PCIe, extract the data, process it and send it back to the root ZCU102(B) again over PCIe. Is this possible to implement, provided that the ZCU 102 has only one PS-PCIe block?
2. Instead of the ZCU102(B) as root complex, what all Xilinx US+MPSOCS can be used?