05-23-2019 03:20 AM
I am designing a PCIe addon card with XCZU21DR. Its a x4 lane board. The power supply to the board will be sourced through a Server SMPS 12V connector. ( not using 12V power pins of PCIe edge connector). Please check the attached schematic for connections. I have following doubts :
1. Switch ON the server power button --> Add on board will be powered up by SMPS instanlty --> after some boot time Server will be up : Will the card be detected in this case?
2. If I power cycle the board while being inserted & Server running : will the card be detected ?
3. If I restart the server while board being in the slot & powered up : What will happen ?
How can I make sure that in case 2 board will be detected ? (I envisage case 2 as : Different bitstreams will be frequqently downloaded while in development phase).
Is there any chance that the board might go bad ?
05-23-2019 07:42 PM
As 1 and 3, the card is powered from the server before, the card should be detected. However, In case 2, the configuration information in the card is lost but the host system does not setup agian after power cycleing of the card. As a result, the card got not to work after that.
05-23-2019 09:48 PM
Thanks a lot.
Can you suggest me how to make case 2 work ?
It will very frustrating to restart the server everytime after loading bitstream( while in development phase).
05-24-2019 12:52 AM
It is impossible that PCIe bus system can detect the bit stream re-loaded FPGA because that the PCIe setup is doen by BIOS or OS. The only way is "Tandem with Field Update" which can replace the user design while PCIe link remains active. However, you have to re-design for the methodoloty and it would frustrate you rather than re-starting the server.
05-27-2019 12:49 AM
Of course it's impossible ... if you don't know how to do it.
There's a whole section in the PCIe standard about hot swap. This needs to read and understood.
I've used it in production designs, with an FPGA (containing a PCIe EP) that wasn't loaded at boot time. This allowed me to boot, then configure the FPGA at my leisure, then trigger the PCIe rescan from software.
My experience is that:
05-27-2019 02:45 AM
Thanks a lot for this perspective.
This seems to be a doable but tough task.
I will update this thread in future after experimenting with it