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jayshu
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Participant
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Registered: ‎06-29-2018

PCIe bifurcation on Zynq Ultrascale+

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We're looking at using the Zynq Ultrascale+ family of parts with the PCIe integrated IP on the device.  Our configuration would be PCIe gen 3 x 8 and was wondering if bifurcation of the bus has been done with this IP?  Our intention is to have 4 lanes to a M2 connector and the other 4 to a PCIe slot.  The IP would be configured as PCIe bridge - root port.

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bethe
Xilinx Employee
Xilinx Employee
941 Views
Registered: ‎12-10-2013

Hi @jayshu,  

 

A single core instantiated in a part cannot be bifrucated down into two connections for the Root Port IP.   This would require a switch in between.   That being said, if you select a part in which you can instantiate 2 AXI Bridge Root Port IPs, you could create them each with a Gen3 x4 connectivity.   This would appear as 2 separate root ports, but that would be a way to do it within a single part. 

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bethe
Xilinx Employee
Xilinx Employee
942 Views
Registered: ‎12-10-2013

Hi @jayshu,  

 

A single core instantiated in a part cannot be bifrucated down into two connections for the Root Port IP.   This would require a switch in between.   That being said, if you select a part in which you can instantiate 2 AXI Bridge Root Port IPs, you could create them each with a Gen3 x4 connectivity.   This would appear as 2 separate root ports, but that would be a way to do it within a single part. 

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post