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Visitor
Visitor
3,887 Views
Registered: ‎10-13-2009

PCIe buffers

hi

i have a query, i read in ug197 (pcie endpoint block in virtex 5) memory requirements for Retry,Tx and Rx buffers, it says it needs minimum of one 36k bits  block RAM for each of these three buffers, and at maximum sixteen 36kbits block RAM each for Tx and Rx buffer and eight 36kbits block RAM for Retry buffer(refer page # 15), furthr it says with increase in payload size the requirement increase.

My question is , does it only to do with payload size , or lane width has also an impact? does this range is given for x1 lane.how the requirement will change , if i use x4 lane?

actually i need to calculate how many block RAMs will left for my logic once i got estimated number of block RAM used for PCIe buffer.

 

can we use or does there is requirement for external memory like DDR2 for that purpose(PCIe buffer)??

 

thankx in advance

 

Madiha

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Scholar
Scholar
3,880 Views
Registered: ‎02-27-2008

As I said in my private reply to your private email:

 

 

I do not know.


Perhaps someone else does, and will reply.

 

I apologize for not being able to answer this one,

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
3,827 Views
Registered: ‎08-07-2007

Hi,

 

In order to use the intergrated block for PCI Express in Virtex-5 device you must use the Block Plus Endpoint wrapper core. This wrapper automatically takes care of the BRAM sizing for you. It supports a  MPS maximum of  payload of 512 bytes. It uses a 6 BRAMS for any lane width and the number of BRAMS does not change regardless of MPS in use up to 512 bytes.

 

See more information about the wrapper here:

 http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v5pciexpressblockplus.htm

 

Regards

John

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