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Visitor
Visitor
4,534 Views
Registered: ‎08-19-2010

PCIe core R/W latency

Hello,

 

I have recently tested ML555 xilinx board with the generated PCIe example design.

I have tried to measure the latency on R or W operation using 2 different systems. (One I7 and one C2D )

Though the results differ a little I have achieved a 1000 ns on Read and 400 ns on Write.

With an Nvidia PCIe card the results are 600 ns on R and 100 ns on W.

The PCIe was Logicore Block Plus v 1.11 using ISE 12.1

 

Am I doing something wrong but on an old PCI design W latency was also arr. 100ns.

I had a look inside the example design and could not find anything that can lead to increased latency.

Is there a way to lower access  latency?

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Xilinx Employee
Xilinx Employee
4,519 Views
Registered: ‎08-06-2008

Re: PCIe core R/W latency

How are you measuring the latency? Is it the time through the GTP and the PCIe core or it involves the user application as well? I would suggest to check the latency in simulation. You could check for 'FB' (start of TLP) at GTP interface and then look for the corresponding trn_rsof at the trn interface. The difference in time between these two points will give you the latency through the core.

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Visitor
Visitor
4,511 Views
Registered: ‎08-19-2010

Re: PCIe core R/W latency

I am mapping to memory ( mmap() )all the suitable BARs and then measuring the memory transfer to that region with a simple program.

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