02-17-2011 04:22 PM
Just to check if I send configuration command to endpoint to send legacy interrupt to root port, what is the response from root port? Can I see anything from the RTL simulation? Will any of the configuration registers reflect the interrupt status? Thanks
02-17-2011 05:40 PM
My understanding of the "Legacy" interrupt is that you treat it like a level-triggered interrupt
from the old (legacy) PCI bus. On PCIe, there is a signal sent to the root port to say you
are asserting the interrupt, and another you send to say you are de-asserting the interrupt.
There is no "interrupt acknowledge" from the root port. It is up to the software that
handles the interrupt to send a signal back to your interrupting device to say that
the interrupt has been handled. Usually this is implemented as a register write
to the interrupting device's register space. This write would then signal your
logic to de-assert the interrupt. There are other approaches as well. For example you
may have a FIFO collecting serial input data and assert the interrupt whenever the
FIFO is not empty. When the root port has read all elements of the FIFO, then the
interrupt would be de-asserted.
02-19-2011 07:52 PM
Thanks for your explanation. So the configuration space will not have a bit to signal that the endpoint has assert the legacy interrupt? Thanks
02-20-2011 01:13 PM
The PCI Configuration Space should assert the interrupt status bit of the status register when a legacy interrupt is asserted. This is bit 3 of the status register. You can find this information in the PCI Spec. Once the deassert packet is sent, that's when this same bit gets cleared. The root shouldn't have to do anything.
The unfortunate news is that this is not functioning correctly as described in the following answer record: