05-07-2019 08:20 AM
Kintex 7 325T ffg900-2 (idcode 43651093)
PCIe endpoint : x4, 5GT/s, ref clock 100MHz, axi clk : 125MHZ/128bits, max payload size 512
Simulation OK : read / write registers, interrupts
On board :
LSPCI values seems ok (number of BAR, size of BAR…)
A PCIe reads return always ffffffff : s_axis_tx_tready is always set to 0 on Pcie interface (after few reads commands, PCIe bus is blocked)
We can see with debugger after startup, a pulse on :
Is it normal ?
Is it the L0s state ?
When we send a read command on PCIe, everything seems OK (data from user code is placed on s_axis_tx_tdata and s_axis_tx_tvalid is activated, both stays to 1) but s_axis_tx_tready don’t change to 1 and return value is ffffffff.
I don’t know where search (vhdl, IP PCIe configuration, OS…) ?
05-08-2019 01:42 AM
cfg_to_trunoff is asserted is telling us that the host send an MSG of Power managment
EP need to response to that message it is expected that the core will goes to lower power status and not response to any TLP request
05-13-2019 04:17 AM
What wake up the EP ? :
* an access of the root ? (read access must automatically wake up the EP ?)
* is the "cfg_pm_wake" must be asserted before put read data on tx_.... ?