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Observer praful.r
Observer
564 Views
Registered: ‎08-09-2018

PCIe example design simulation issue

Hi,

I am using xilinx PCIe gen 3 subsystem. I have opened the example project and tried to simulate the one. Unfortunately only one read and write is happening through PCIe-AXI. How can I increase the number of read and write in the PCIe-AXI? Is there any parameter to change in example design? pls help

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2 Replies
Xilinx Employee
Xilinx Employee
505 Views
Registered: ‎12-10-2013

Re: PCIe example design simulation issue

Hi @praful.r,

 

Are you targeting the AXI Bridge functionality?  Are you Root Port or Endpoint? 

 

For the Endpoint benches, you will want to modify the sample_tests.vh file to add more read and write.  We provide TSKs in the tx_usrapp source on the RP model to achieve this.

 

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Observer praful.r
Observer
443 Views
Registered: ‎08-09-2018

Re: PCIe example design simulation issue

Thank you very much.. It worked as per your suggestion

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