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yonigo
Visitor
Visitor
8,192 Views
Registered: ‎10-14-2014

PCIe example desing synthesis

Im trying to get the pcie gen3 example design to work, but i cant seem to implement it and see somthing with lspci.

If i use vivado (i prefer not to at this point) to create the example design then implement it and upload it to the fpga, i dont see anything when i use lspci. Whas i supposed to change something in the code or pin assignment?

I also tried to run the implement.sh script and upladed the routed.bit file created. still nothing on lspci.

If i try to use ise, i get this error:

ConstraintSystem:59 - costraint <NET "ext_clk.pipe_clock_i/CLK_TXOUTCLK" TNM_NET = "SYSCLK" ;> ... net not found...

What am i doing wrong? i want to see everything run on the fpga and to see it with lspci before i continue.

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vsrunga
Xilinx Employee
Xilinx Employee
8,187 Views
Registered: ‎07-11-2011

Hi,

 

Please check this link for discusison on similar error

http://forums.xilinx.com/t5/7-Series-FPGAs/PCIe-to-DDR3-Targeted-Reference-Design-did-not-synthesize/m-p/549157#M7266

 

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kotir
Scholar
Scholar
8,172 Views
Registered: ‎02-03-2010

Hi,

 

You need to check the pin assign ments and GT locations to match with your board.

 

Regarding the warning of unable to find net, if this is your own design , then you need to check the hierarchy specified int he constraint.

 

Regards,

KR

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