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tony_tse
Visitor
Visitor
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Registered: ‎01-06-2021

PCIe is link up,but link width is not right

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Hello,

I used ISE14.7 to implement on a xc7k325T-2FFG900 device on a PCIe hard core(5.0GT,8Lane), When I plug into motherboard, link up signal is ready,and the motherboard can recognize the board,but the link width is not always right.sometimes it's right,but sometimes it only recognize the link width is only 4.

PCIE_2.png

I go through AR56616's pdf ,it said this issue was resolved by adding a resistor on the board trace that allowed the RP to correctly detect receiver on all lanes.(Page 58),but it didn't point out how/where to add, can anyone tell me ?

Thank you.

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nmanitri
Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎06-13-2018

Hi @tony_tse ,

You need to check the termination resistor. Is correctly added in the board or NOT? 
Please refer PCB user guide for better understanding.

https://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

Regards,

Naveen 

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nmanitri
Xilinx Employee
Xilinx Employee
225 Views
Registered: ‎06-13-2018

Hi @tony_tse ,

You need to check the termination resistor. Is correctly added in the board or NOT? 
Please refer PCB user guide for better understanding.

https://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

Regards,

Naveen 

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