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Visitor philipp
Visitor
757 Views
Registered: ‎12-18-2017

PCIe lane order with DMA/Bridge Subsystem for PCI Express

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Hi,

 

i am using the ip core "DMA/Bridge Subsystem for PCI Express" for my xc7a200tfbg484-2 device and want to change the lane order. Every time when i changed the lane order in "I/O Ports" tab to my physical order, it will be changed after synthesis and implementation automatically.

 

In my opinion the .xdc file ("...pcie2_ip-PCIE_X0Y0.xdc") of the ip sources fix lane with the MGT pin. Can i changed the mapping between MGT pins and pcie lanes?

 

I have also found the keywoard "DISABLE_LANE_REVERSAL". I set it to FALSE but, when i synthesis the ip core the value will be changed.

 

How can I changed the mapping between MGT and pcie lane order?

 

Thanks

 

 

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Xilinx Employee
Xilinx Employee
793 Views
Registered: ‎08-02-2007

回复: PCIe lane order with DMA/Bridge Subsystem for PCI Express

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Yes you can change  the code in("...pcie2_ip-PCIE_X0Y0.xdc") of the ip sources fix lane with the MGT pin.

you can run

set_property  is_locked true  [ get_files xxx.xci] 

modify the code with other editor

and reload the xci file in vivado

 

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3 Replies
Xilinx Employee
Xilinx Employee
794 Views
Registered: ‎08-02-2007

回复: PCIe lane order with DMA/Bridge Subsystem for PCI Express

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Yes you can change  the code in("...pcie2_ip-PCIE_X0Y0.xdc") of the ip sources fix lane with the MGT pin.

you can run

set_property  is_locked true  [ get_files xxx.xci] 

modify the code with other editor

and reload the xci file in vivado

 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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Moderator
Moderator
697 Views
Registered: ‎02-16-2010

回复: PCIe lane order with DMA/Bridge Subsystem for PCI Express

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Check if this thread helps.
https://forums.xilinx.com/t5/PCI-Express/Some-questions-about-PCIE-lanes-exchange-inside/m-p/877821#M11643
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Visitor philipp
Visitor
687 Views
Registered: ‎12-18-2017

回复: PCIe lane order with DMA/Bridge Subsystem for PCI Express

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Thanks for your reply.

 

Yes you can change  the code in("...pcie2_ip-PCIE_X0Y0.xdc") of the ip sources fix lane with the MGT pin.

you can run

I have modified the .xdc file that you have mentioned and i have successfully changed the mapping between lanes and MGT pins. But I get bus error on the pcie on my own designed board. Can i excluded the ip core. On the Evalboard AC701 it is already running.

 

set_property  is_locked true  [ get_files xxx.xci] 

modify the code with other editor

and reload the xci file in vivado

But I dont understand your following post. That is only for locking the ip core version? The functionality doesnt change?

 

 

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