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JoaoGarrido
Visitor
Visitor
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Registered: ‎04-07-2021

PCIe not detected on ZCU106

Evaluation Board: Xilinx ZCU106

Toolchain version:

  • Vivado 2020.2
  • Petalinux 2020.2
  • Vitis 2020.2

Example Design Tested:

  • Xilinx Answer 72076 - UltraZed Endpoint Design in Vivado (Standalone and Linux Version)
  • UltraScale+ Devices Integrated Block for PCI Express Example Design (Open IP Example Design)


Tested on 2 different Host systems

  • Host system 1:
    • Ubuntu 18.04 LTS and Ubuntu 20.04 LTS
    • Gigabyte B450M
    • Ryzen 5 2600
    • 16 GB RAM
  • Host system 2:
    • Ubuntu 18.04 LTS and Ubuntu 20.04 LTS
    • HP 3397
    • i3 4130
    • 8 GB RAM


Problem:

  • The host system can't detect the PCIe endpoint (ZCU 106) on a Link Layer Level.
  • Running $ lspci or $ dmesg on the host system doesn't report any Xilinx or unknown PCIe.
  • Both examples were tested with x1 and x4 lanes and the same result was observed.
  • While running the standalone example(pcie_ep_pio.c) for the Xilinx Answer 72076 example, could verify that the design was running by connecting over the UART interface. The last message shown was "Waiting for PCIe Link up".
  • Tried to do a warm reboot with both designs to eliminate issues related to the programming time of the FPGA.

Any idea how to solve this issue?

EDIT:
Followed the following tutorial Getting to link up with pci express in ultrascale+ and obtained the result on the next image:
PCIe_debug_result_16_15__14_21_2021.png

Together with BER for Link 0:

IQ_scan.png

The result was the same after a warm reboot. The device was programmed and booted from JTAG.


Thanks in advance,
João Garrido

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pvenugo
Moderator
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217 Views
Registered: ‎07-31-2012

Hi @JoaoGarrido ,

 

I hope you are using PL PCIe. Could you please share the XCI file so that I can test its generated example at my end?

It should work unless PL PCIe clock in not propagated properly.

 

Regards

Praveen


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JoaoGarrido
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Registered: ‎04-07-2021

Hi

Last Friday, it worked with Integrated Ultrascale PCIe and XDMA IPs examples.
Still having issues with the Xilinx Answer 72076 example where it isn't detected. Any advice on how to move forward?

Regards,
João Garrido

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pvenugo
Moderator
Moderator
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Registered: ‎07-31-2012

Refer to AR# 71493: PetaLinux Image Generation and System Example Design with ZCU102 PS-PCIe as Root Complex and ZC706 as Endpoint (xilinx.com) 


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JoaoGarrido
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Registered: ‎04-07-2021

Hi,

Thanks for the answer but I want to create a PS-PCIe Endpoint design and that example is for Root Complex design.
The Xilinx Answer 72076 has both but, after following the instructions of the endpoint design, the endpoint is not detected.

Regards,
João Garrido

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hxiaoqiang
Explorer
Explorer
87 Views
Registered: ‎11-09-2015

hi, can you share the AR 's example code,the  Xilinx Answer 72076 page can't open right now.

BRs

HSQ

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