04-13-2021 08:41 AM - edited 04-14-2021 08:29 AM
Evaluation Board: Xilinx ZCU106
Example Design Tested:
Tested on 2 different Host systems
Any idea how to solve this issue?
Followed the following tutorial Getting to link up with pci express in ultrascale+ and obtained the result on the next image:
Together with BER for Link 0:
The result was the same after a warm reboot. The device was programmed and booted from JTAG.
Thanks in advance,
04-19-2021 11:05 AM
Hi @JoaoGarrido ,
I hope you are using PL PCIe. Could you please share the XCI file so that I can test its generated example at my end?
It should work unless PL PCIe clock in not propagated properly.
04-19-2021 11:18 AM
Last Friday, it worked with Integrated Ultrascale PCIe and XDMA IPs examples.
Still having issues with the Xilinx Answer 72076 example where it isn't detected. Any advice on how to move forward?
04-21-2021 07:34 AM
04-22-2021 07:29 AM
Thanks for the answer but I want to create a PS-PCIe Endpoint design and that example is for Root Complex design.
The Xilinx Answer 72076 has both but, after following the instructions of the endpoint design, the endpoint is not detected.